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Multi-level cell (MLC) NAND flash memories are very popular storage media because of their power efficiency and big storage density. This paper proposes to use nonlinear t-error-correcting codes to replace linear BCH codes for error detection and correction in MLC NAND flash memories. Compared to linear BCH codes with the same bit-error correcting capability t, the proposed codes have less errors...
In the AES algorithm, the Substitution Box (S-Box) often dominates the area and delay of implementations. The S-Box performs a byte-wise substitution on the data based on an established code book, and most AES algorithm implementations use a large complex logic block consisting mainly of XORs to implement the S-Box. Direct implementation of the S-Box with a look-up table (LUT) has been eschewed due...
This paper presents and evaluates six novel, low-power, FinFET-based design schemes of the conventional NOR address decoder. These schemes differ in front- and back-gate connections and input signal swing. Simulations of these schemes were performed using a 32nm FinFET technology model and the schemes' performance was evaluated in terms of dynamic current consumption, delay, and leakage current consumption...
Variations of process parameters have an important impact on reliability and yield in deep sub micron IC technologies. One methodology to estimate the influence of these effects on power and delay times at chip level is Monte Carlo Simulation, which can be very accurate but time consuming if applied to transistor-level models. We present an alternative approach, namely a statistical gate-level simulation...
As the microprocessor speed increases from 500MHz to 1GHz and beyond, SOC designers are forced to innovate new schemes in their use of cache memory for high speed access. In this paper, clock to wordline path delay is optimized using a novel circuit design technique. Using this novel circuit, clock to word line path delay is optimized by 2.5 times at worst case corner. For a typical memory instance...
A completely new scheme for quaternary logic is proposed. Instead of conventional fuzzy logic or Galois Field theory, the logic system is based on the extension of Boolean algebra. The logic is capable of handling both quaternary and coupled-binary inputs, where binary operands are coupled in pairs to form quaternary entities. All necessary operators are defined and several theorems and properties...
The neuron MOS transistor (neuMOS) is a new device with multi-input gates and one floating gate. It is capable of obtaining a weighted sum calculation of multi-input gates signals and then operating the threshold based on the result of summation, thereby simulating the function of biological neurons. The neuron MOS transistor' characteristics about multiple input gates and the floating gate capacitance...
A Goldschmidt iterative divider for quantum-dot cellular automata (QCA) is designed using a new architecture that solves a problem that arises in implementing conventional state machines in QCA. State machines for QCA often have synchronization problems due to the long delays between the state machines and the units (i.e., the computational circuits) to be controlled. To resolve this problem, a data...
SOC designs for consumer electronics often evolve generation by generation in a very short time. Besides the needs for merging more functionality, more and more enhancements are for the purpose of interface upgrading for new standards and better or faster signal processing hardware engines for video/audio encoding and decoding. Physical designs for these kinds of enhanced chips can reuse large potions...
An adiabatic 32 times 32 content-addressable memory (CAM) are designed in this paper, which consists of a CAM storage-cell array, address decoders, bit-lines drivers, and match-line driving circuits. All circuits except for CAM storage cells and driving control circuits for match lines are realized using CPAL (complementary pass-transistor adiabatic logic) circuits. The charge of large node capacitances...
High throughput architecture of an encoder and a decoder for a quasi-cyclic low-density parity-check (LDPC) code is proposed. A new systematic encoding method is carried out by polynomial manipulation. The proposed decoder architecture, where the check-node process is split into two processes so that the memory access becomes column-wise, enables overlapped message-passing for any parity-check matrix...
A 32 times 32 register file based on complementary pass-transistor adiabatic logic (CPAL) has been fabricated with chartered 0.35 mum process. All the circuits except for the storage cells employ CPAL circuits. The storage cell is based on the conventional memory one. For comparison, a conventional 32 times 32 register file is also embedded in the chip. Full-custom layouts are drawn. The energy and...
In this paper, we propose a novel multi-code turbo decoder architecture for 4G wireless systems. To support various 4G standards, a configurable multi-mode MAP (maximum a posteriori) decoder is designed for both binary and duo-binary turbo codes with small resource overhead (less than 10%) compared to the single-mode architecture. To achieve high data rates in 4G, we present a parallel turbo decoder...
We propose an on-line testing approach for the control logic of high performance microprocessors. Rather than adding information redundancy (in the form of error detecting codes), we propose to look for the information redundancy (referred to as function-inherent codes) that the microprocessor control logic may inherently have, due to its required functionality. We will show that this allows to achieve...
This paper proposes the design of a FPGA configurable logic block (CLB) using asynchronous static NULL convention logic (NCL) Library. The proposed design uses three static LUT's for implementing NCL logic functions. Each LUT can be configured to function as any one of the 27 fundamental NCL Static gates. The proposed CLB supports 10 inputs and three different outputs, each with resettable and inverting...
This paper proposes the design of a FPGA configurable logic block (CLB) using asynchronous semi-static NULL convention logic (NCL) Library. The proposed design uses three semi-static LLT's for implementing NCL logic functions. Each LLT can be configured to function as any one of the 27 fundamental NCL Semi-Static gates. The proposed CLB supports 10 inputs and three different outputs, each with resettable...
Low power consumption is a key requirement in mobile and other embedded applications. Accurate power estimation during design phase is a key enabler for designing a power optimized SoC. Abstracting accurate power models for complex IPs such as embedded memories is a challenging task. At the same time, the complex modules have a large share in total power consumption of an IC. In this paper we analyze...
This paper presents a technique for efficient gate-level realization of strongly indicating function blocks. For the function block implementing the desired logic, the input state space explodes as it expands exponentially for even a gradual increase in the number of inputs. In this context, a novel design-methodology for realizing non-regenerative logic as a function block, under the discipline of...
As integrated circuit technology plumbs ever greater depths in the scaling of feature sizes, maintaining the paradigm of deterministic Boolean computation is increasingly challenging. Indeed, mounting concerns over noise and uncertainty in signal values motivate a new approach: the design of stochastic logic, that is to say, digital circuitry that processes signals probabilistically, and so can cope...
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