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The presented paper is based on a new technology, QCA (Quantum-dot Cellular Automata), a promising successor for CMOS transistor technology. The implementation of logic circuits by the traditional devices (eg. transistors, diodes and resistors are replaced by quantum devices (quantum dots or single domain nano magnets). The use of quantum-dots is a promising emerging technology for implementing digital...
Quantum codes excel at correcting local noise but fail to correct leakage faults that excite qubits to states outside the computational space. Aliferis and Terhal have shown that an accuracy threshold exists for leakage faults using gadgets called leakage reduction units (LRUs). However, these gadgets reduce the threshold and increase experimental complexity, and the costs have not been thoroughly...
The quantum computing represents a new field, which is still being researched, that may have numerous applications in the computer arithmetic, in the encryption - decryption systems, rapid search algorithms and physical systems' emulations. The hardware device that can make this type of calculations is still expensive nowadays and the number of the manufacturers is reduced. On the other hand, the...
This paper describes a fully-integrated 77-GHz distant-selective pseudo-random noise coded Doppler radar transceiver in a Silicon-Germanium technology. The transceiver is capable of measuring a vibration or a velocity of a target at a specified distance, which is programmable and can be configured very precisely in the transceiver, and suppressing all other targets elsewhere. It is equipped with two...
The Reed-Solomon (RS) codes are widely used in communication systems and data storages to recover data from possible errors that occur during transmission and from disk error respectively. This paper describes a new method for error detection in the Chien Search block of RS decoders. The main feature of this method is to introduce a factorization of the error locator polynomial, which allowed us to...
A Memristor is a nonlinear resistor with memory, and is considered as the fourth type of basic circuit element except resistor, capacitor and inductor. With special circuitry characteristics, memristor can be used for both information storage and logic operations. In traditional Von Neumann computer architecture, address decoder is an important component connecting processor and memory. This paper...
Content Addressable Memory (CAM) is a data storage device, utilizing the Static Random Access Memory (SRAM) cell. CAMs are very popular especially implemented in network routers for IP address lookup, packet forwarding and packet classifications. Up to now, there are many types of CAM to conform to these different implementations. For the purpose to estimate the efficiency and power distribution of...
This paper presents and evaluates six novel, low-power, FinFET-based design schemes of the conventional NOR address decoder. These schemes differ in front- and back-gate connections and input signal swing. Simulations of these schemes were performed using a 32nm FinFET technology model and the schemes' performance was evaluated in terms of dynamic current consumption, delay, and leakage current consumption...
Variations of process parameters have an important impact on reliability and yield in deep sub micron IC technologies. One methodology to estimate the influence of these effects on power and delay times at chip level is Monte Carlo Simulation, which can be very accurate but time consuming if applied to transistor-level models. We present an alternative approach, namely a statistical gate-level simulation...
In this paper the design and simulation of a single-electron 2-4 decoder based on NAND gates is presented. The simulation was made using a Monte-Carlo based tool. The results confirmed that the circuit was behaving as a 2-4 decoder. The stability plot and the free energy history diagrams offer detailed analysis of the circuit. The results were compared to similar circuits reported in the literature...
Multiple valued logic (MVL) has been gaining popularity and practical applications. In addition to the standard MVL benefits, quaternary logic offers the benefit of easy interfacing to binary logic due to the fact that the radix 4 = 22 allows for simple encoding/decoding circuits. Quaternary cells based on the Supplementary Symmetrical Logic Circuit Structure (SUSLOC) are modeled and used for our...
The quantum well MODFET (QWMODFET) has two 2DEG layers. We paralleled these two thin layers by using diffused Au/Ge/Ni ohmic contacts. Two back and top controlling gate were used on both sides of the structure to control the switching property of 2DEG layers separately. In this case there are two transistors in the same position. An enhancement mode QWMODFET was used to design some basic gates such...
This paper presents a low-power test scheme by using random single input change (RSIC) technique. By adding simple control logic on original linear feedback shift register (LFSR), the output of LFSR is modified, and RSIC test sequence can be generated. The new RSIC sequence optimizes the switching activity of circuit-under-test (CUT), and then result in decrease of test power consumption. Initially,...
A novel scheme for reducing the test application time in accumulator-based test-pattern generation is presented. The proposed scheme exhibits extremely low demand for hardware. It is based on a decoder whose inputs are driven by a very slow external tester. Experimental results on ISCAS benchmarks substantiate a test-time reduction of 75%-95% when compared to previously published test-set embedding...
In this paper, we present a systematic method for the designing fault tolerant reversible arithmetic circuits for finite field or Galois fields of the form GF(2m). To tackle the problem of errors in computation, we propose error detection and correction using multiple parity prediction technique based on low density parity check (LDPC) code. For error detection and correction, we need additional garbage...
In this paper a BISR architecture for embedded memories is presented. The proposed scheme utilises a multiple bank cache-like memory for repairs. Statistical analysis is used for minimisation of the total resources required to achieve a very high fault coverage. Simulation results show that the proposed BISR scheme is characterised by high efficiency and low area overhead, even for high defect densities...
Performance evaluation techniques for fundamental graphics algorithms and for algorithms to be used in multimedia and embedded systems are investigated. Models of computation considering only arithmetic and logic operations taken on input data are regarded as inadequate for processors with instruction-level parallelism. For experimental evaluation of graphics algorithms clock-cycle counting is found...
In this paper, we present an automatic soft IP (Intellectual Property) generation method for high-speed Viterbi decoders. In our scheme, the synthesizable HDL (Hardware Description Language) code for the Viterbi decoder is automatically produced depending on not only the system parameters such as a coding rate but also the hardware architecture for parallel processing. The proposed method is implemented...
Low power consumption is a key requirement in mobile and other embedded applications. Accurate power estimation during design phase is a key enabler for designing a power optimized SoC. Abstracting accurate power models for complex IPs such as embedded memories is a challenging task. At the same time, the complex modules have a large share in total power consumption of an IC. In this paper we analyze...
Video-streaming can now be offered on third-generation (3G) mobile networks. Most research efforts have focused on video download. This paper presents a detailed study of challenges faced for successfully deploying applications requiring life video upload. Both subjective and objective qualities as well as the effects of mobility are analyzed on real 3G networks. Consequently, video profiles are identified...
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