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In recent trends of VLSI technology the reversible logic has became the major area of research in optimization of area, power and speed constraints. The reversible logic has equal number of inputs and outputs. In wireless communications Viterbi algorithm is employed to have minimal number of communication channels. The Viterbi decoder design at 65nm technology using reversible logic has made an attempt...
This paper demonstrates the reversible logic synthesis for the n-to-2n decoder, where n is the number of data bits. The circuits are designed using only reversible fault tolerant Fredkin and Feynman double gates. Thus, the entire scheme inherently becomes fault tolerant. Algorithm for designing the generalized decoder has been presented. In addition, several lower bounds on the number of constant...
As a result of technology scaling and higher integration densities there may be variations in parameters and noise levels which will lead to larger error rates at various levels of the computations. As far as memory applications are concerned the soft errors and single event upsets are always a matter of problem. The paper mainly focuses on the design of an efficient Majority Logic Detector/Decoder...
In the modern era of electronics and communication decoding and encoding of any data(s) using VLSI technology requires low power, less area and high speed constrains. The viterbi decoder using survivor path with necessary parameters for wireless communication is an attempt to reduce the power and cost and at the same time increase the speed compared to normal decoder. This paper presents three objectives...
A high-performance 128-input CMOS multiplexer (MUX) tree is designed in this study. In order to enhance the speed, the high-speed feature of traditional transmission-gate MUX circuits and CMOS MUX circuits are integrated to the 128-to-1 MUX tree with high transmission speed. The circuit simulation in the CMOS 0.18μm process presents 26% reduction of delay time, comparing to the 128-to-1 MUX tree composed...
In this work we introduce a hybrid CLA-Ripple Power-aware adder (or simply HICPA) for high performance processors. HICPA is a multi-component adder that saves power by avoiding aggressive usage of the Carry Look-Ahead adder for add operations using small operands. Instead, for small size operands, HICPA uses a small and power efficient Ripple Adder. We evaluate HICPA using a subset of SPEC'2K benchmarks...
As technology continues to scale, reducing leakage is critical to achieve energy efficiency. Power gating can potentially save a significant part of leakage but it incurs both energy and performance penalties. Therefore, power gating decisions need to be made carefully. In the current low-power SoC design, an IP core is power gated when it is not operating. In this paper, we explore the IP idle time...
Reversible logic is an emerging nanotechnology used in the design and implementation of nanotechnology and quantum computing with the main goal of reducing physical entropy gain. Significant work have been produced in the design of fundamental reversible logic structures and arithmetic units, and recent developments in sequential design of reversible circuits has opened new avenues in the implementation...
Reversible computation differs from traditional computation in that it preserves information while manipulating it. This new design paradigm has very attractive thermodynamic consequences and holds many applications in current and emerging technologies. Modern computers can reduce power consumption by taking advantage of reversibility, and quantum computers operate reversibly. Researchers have already...
Reversible logic is an emerging nanotechnology widely being considered as the potential logic design and implementation of nanotechnology and quantum computing with the main goal of reducing physical entropy gain. Recent advances in reversible logic allow for new avenues in the implementation of reversible combinational circuits. Part of this advancement is the design and implementation of a finite...
We present an energy-reduction strategy for applications which are resilient, i. e. can tolerate occasional errors, based on an adaptive voltage control. The voltage is lowered, possibly beyond the safe-operation region, as long as no errors are observed, and raised again when the severity of the detected errors exceeds a threshold. Due to the resilient nature of the applications, lightweight error...
In this paper we address the issue of improving ECC correction ability beyond that provided by the standard SEC/DED Hsiao code. We analyze the impact of the standard SEC/DED Hsiao ECC and for several double error correcting (DEC) codes on area overhead and cache memory access time for different codeword sizes and code-segment sizes, as well as their correction ability as a function of codeword/code-segment...
This paper presents and evaluates six novel, low-power, FinFET-based design schemes of the conventional NOR address decoder. These schemes differ in front- and back-gate connections and input signal swing. Simulations of these schemes were performed using a 32nm FinFET technology model and the schemes' performance was evaluated in terms of dynamic current consumption, delay, and leakage current consumption...
A decoder is a hardware module that expands an x-bit input into an n-bit output, where x ?? n. It can be viewed as producing a set P of subsets of an n-element set Zn. If this set P can be altered by the user, the decoder is said to be configurable. In this paper we propose a class of configurable decoders (called ??mapping-unit?? based decoders or simply MU-decoders) that facilitate efficient selection...
In a flash ADC, output of the comparators constitute the thermometer code. This thermometer code is converted to binary code with the help of a thermometer to binary decoder using a ROM. However, this conversion scheme suffers from metastability and bubble errors. A novel ROM architecture has been proposed which suppresses metastability, both first and second order bubble errors. It eliminates the...
This paper proposes a new switch box architecture in SRAM-based FPGAs to mitigate soft error effects. In this switch box architecture, the number of SRAM bits required for programming switch box is reduced to 67% without any impact on routing capability of the switch box. This architecture does not require any modification of the existing placement and routing algorithms. The architecture was evaluated...
Variations of process parameters have an important impact on reliability and yield in deep sub micron IC technologies. One methodology to estimate the influence of these effects on power and delay times at chip level is Monte Carlo Simulation, which can be very accurate but time consuming if applied to transistor-level models. We present an alternative approach, namely a statistical gate-level simulation...
As the microprocessor speed increases from 500MHz to 1GHz and beyond, SOC designers are forced to innovate new schemes in their use of cache memory for high speed access. In this paper, clock to wordline path delay is optimized using a novel circuit design technique. Using this novel circuit, clock to word line path delay is optimized by 2.5 times at worst case corner. For a typical memory instance...
Due to the rapid decrease of technology feature size speed related faults, such as Address Decoder Delay Faults (ADDFs), are becoming very important. In addition, increased leakage currents demand for improved tests for Bit Line Imbalance Faults (BLIFs)(caused by memory cell pass transistor leakage). This paper contributes to new and improved algorithms for detecting these faults. First it provides...
An on-chip high-speed 4-bit BCH decoder for error correcting in a MLC NOR flash memory is presented. As process shrinking beyond 45nm, double-error-correcting (DEC) BCH code is needed for reliability requirement. A novel fast-decoding algorithm is developed by eliminating finite field divisions and combining arithmetic operations. As a result, the decoding latency is significantly reduced by 80%....
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