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Field Programmable Gate Arrays (FPGAs) have proven their potential in accelerating High Performance Computing (HPC) Applications. Conventionally such accelerators predominantly use, FPGAs that contain fine-grained elements such as LookUp Tables (LUTs), Switch Blocks (SB) and Connection Blocks (CB) as basic programmable logic blocks. However, the conventional implementation suffers from high reconfiguration...
This paper presents a new hardware architecture for pattern detection and classification specific for human face detection including raw image acquisition, integral image creation, window extraction, pyramid generation, and detection algorithms in simultaneous steps. The detection part of the face is implemented in a reconfigurable way by providing different paths for either Viola-Jones or block LBP...
Keystroke dynamic is one of the behavioral biometric identification techniques which distinguish users through their unique typing style. This paper presents two techniques to measure the distance metric between two samples of the same user. Two methods are used to implement the normalized distance between two samples of the same user; first method uses JavaScript for measuring the feature extraction...
Real-time object detection is important for surveillance applications. This paper describes a high-performance object detector using a commercially available FPGA. Major bottlenecks in the real AdaBoost classifier are resolved. A new FIR-filter-like hardware architecture takes advantage of an FPGA's hardware parallelism and block-RAM structure. The resulting design uses Xilinx Virtex 5 and achieves...
Some computationally complex problems require complex solutions in terms of number of processors and diversity of computation methods. Metabolic systems are naturally capable of solving complex problems; they are mathematically modelled with hundreds of differential equations. In order to understand those metabolisms or simply replicate their functions in engineering problems, we need a large network...
Considering the vast requirement of embedded fingerprint identification system, a new fingerprint identification system based on SOPC is proposed. FPGA is the core of the system, Nios II processor is created in FPGA. Custom instructions are used to implement the algorithm of fingerprint image processing, the speed of fingerprint identification is improved with custom instruction. The system has some...
Pedestrian detection is a crucial task in several video surveillance and automotive scenarios, but only a few detection systems are designed to be realized on an embedded architecture, allowing to increase the processing speed which is one of the key requirements in real applications. In this paper, we propose a novel SoC (System on Chip) architecture for fast pedestrian detection in video. Our implementation...
In this paper we propose a hardware solution by the use of FPGA based circuit for real time face detection. We have built a sub-window architecture for the extraction of Haar-like features, which are the basic elements of weak classifiers according to AdaBoost learning algorithm. The main contribution is that the proposed architecture removes traditional frame buffer, and only reserve the line buffer...
Iris Identification is nowadays one of the most promising techniques in Authentication. Most modern iris recognition systems are currently deployed on traditional sequential digital systems, such as a simple DSPs or MIPS processor. However, in this method, we can only match each data one by one, which will waste much time. In this study, iris matching, a repeatedly executed portion of a modern iris...
Co-occurrence histograms of oriented gradients (CoHOG) is a powerful feature descriptor for pedestrian detection. However, its calculation cost is large because the feature vector for the CoHOG descriptor is very high-dimensional. In this paper, in order to achieve real-time detection on embedded systems, we propose a novel hardware architecture for the CoHOG feature extraction. Our architecture exploits...
This paper introduces an embedded speech recognition system, including both hardware and software frameworks, based on an FPGA platform and the HMM algorithm. The paper also proposes an approach to the design and implementation of an IP core for the forward algorithm, as well as simulating the algorithm. The main advantage of this approach is the reduction of processing time in speech recognition...
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