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A simulation of the Board Level Drop-Test is performed to evaluate some WL-CSP (Wafer-Level Chip-Scale Packages) performances. An elastic-plastic model is applied on both solder bump and copper pad materials. It intends to demonstrate that copper plasticity is mandatory due to the large plastic strain occuring in these materials. A statistical analysis discusses the required accuracy for the modeling...
3-D technologies open a wide range of chip integration possibilities for microelectronic systems. Most of these technologies are using through-silicon vias (TSV). One disadvantage of this technology is the high investment for new equipment and processing cost for Si etching and metallization. The thin chip integration technology (TCI) presented in this paper is based upon existing WLP infrastrcuture:...
In this study, three examples of failure analyses of electronic packaging by using the finite element method are presented. These are: (1) the failures (delaminations) near the interface between the filled copper and the silicon and between the copper and the silicon dioxide dielectric of the TSV of a 3D system-in-package (SiP) due to the local thermal expansion mismatch between the silicon and the...
Through-silicon vias (TSVs) have garnered a lot of interest in recent years because TSV is a key enabling technology for three dimensional (3D) integrated circuit (IC) stacking, silicon interposer technology, and advanced wafer level packaging (WLP). There has been significant effort in TSV fabrication and electrical design. However, considerably less work has been done on thermo-mechanical analysis...
Through an aggressive product development program which includes experiment and simulation, Amkor has developed the next level of WLCSP (CSPnltrade), a product which exhibits superior board level reliability when subjected to drop impact, a strong requirement for portable electronics. Failure mechanism of WLCSP under drop test has been established. Depending on type of WLCSP and test board design,...
The bump on flexible lead (BoFL) is a chip-to-substrate interconnect technology which uses flexible structures to accommodate the CTE mismatch between the chip and PCB substrate and consequently should be reliable without underfill. To achieve a high flexibility, the lead-free bump is located on a flexible lead. The flexible lead consists of a copper redistribution layer (RDL) embedded in a polyimide-bridge...
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