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This paper examines the role of NBTI and PBTI on SRAM Vmin shifts during HTOL stressing and quantifies their impact on reliability lifetime projections in scaled high-k metal gate (HKMG) technologies. Correlation between measured HTOL SRAM Vmin shifts and transistor level parametrics is summarized on both 28nm poly-SiON and HKMG technologies. The paper concludes that the commonly used HTOL acceleration...
The post fabrication technique for self-improvement of SRAM cell stability is validated by experiment using 1k DMA SRAM TEG array. It is shown that the stability of unbalance cells is automatically improved by merely applying stress voltage to VDD terminal. The mechanism of the phenomena is also analyzed by measuring VTH of all transistors before and after stress and it is newly found that |VTH| of...
A special device-matrix-array (DMA) TEG of 16k bit SRAM cells has been designed. Static noise margins (SNM) and 6 transistors in cells are directly measured and their fluctuations are examined. It is found for the first time that one-side SNM follows the normal distribution up to ±4σ. It is also found that the cell stability is worse than circuit simulation using Vth of measured 6 transistors. Furthermore,...
We present a practical, systematical method for the evaluation of the soft error rate (SER) of microelectronic devices. Existing methodologies, practices and tools are integrated in a common approach while highlighting the need for specific data or tools. The showcased method is particularly adapted for evaluating the SER of very complex microelectronic devices by engineers confronted to increasingly...
Continuous scaling, necessary for enhanced performance and cost reduction, has pushed existing CMOS materials much closer to their intrinsic reliability limits, forcing reliability engineers to get a better understanding of circuit failure. This requires that designers will have to be very careful with phenomena such as high current densities or voltage overshoots. In addition to the reliability issues,...
Transconductance (gm) enhancement in n-type and p-type nanowire field-effect-transistors (nwFETs) is demonstrated by introducing controlled tensile strain into channel regions by pattern dependant oxidation (PADOX). Values of gm are enhanced relative to control devices by a factor of 1.5 in p-nwFETs and 3.0 in n-nwFETs. Strain distributions calculated by a three-dimensional molecular dynamics simulation...
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