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We present a new reliable high-performance interconnection approach destined for complex System on Chip based on the network-centric approach. The originality of our approach is to avoid the lost of data packets, detect routing errors and reduce data packets latency by emptying output buffer when the neighbour router is unavailable. We present the basic concepts of the reliability communication technique...
The continuing advances in processing technology result in significant decreases in the feature size of integrated circuits. This shrinking leads to increases in susceptibility to transient errors and permanent faults. Network on Chips (NoCs) are poised to address the demands for high bandwidth communication among processing elements. The structural redundancy inherited in NoC-based design can be...
High performance, reliability, transient and permanent fault-tolerance, and low energy consumption are major objectives of Networks-on-Chip (NoCs). Since,different applications impose various communication requirements in NoCs, a number of research studies have revealed that the performance advantages of routing schemes are more noticeable on power consumption under different traffic patterns. However,the...
Current trends in technology scaling foreshadow worsening transistor reliability as well as greater numbers of transistors in each system. The combination of these factors will soon make long-term product reliability extremely difficult in complex modern systems such as systems on a chip (SoC) and chip multiprocessor (CMP) designs, where even a single device failure can cause fatal system errors....
In this paper a BISR architecture for embedded memories is presented. The proposed scheme utilises a multiple bank cache-like memory for repairs. Statistical analysis is used for minimisation of the total resources required to achieve a very high fault coverage. Simulation results show that the proposed BISR scheme is characterised by high efficiency and low area overhead, even for high defect densities...
Networks on chips (NoCs) provide a mechanism for handling complex communications in the next generation of integrated circuits. At the same time, lower yield in nano-technology, makes self repair communication channels a necessity in design of digital systems. This paper proposes a reliable NoC architecture based on specific application mapped onto an NoC. This architecture is capable of recovering...
In this paper we propose a set of different configurations of failure recovery schemes, developed for network-on-chip (NoC) based systems. These configurations exploit the fact that communication in NoCs tends to be partitioned and eventually localized. The failure recovery approach is based on checkpoint and rollback and is aimed towards fast recovery from system or application level failures. The...
Network-on-chip (NoC) architectures employing packet-based communication are being increasingly adopted in system-on-chip (SoC) designs. In addition to providing high performance, the fault-tolerance and reliability of these networks is becoming a critical issue due to several artifacts of deep sub-micron technologies. Consequently, it is important for a designer to have access to fast methods for...
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