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Error occurrence in embedded systems has significantly increased. Although inherent resource redundancy exist in processors, such as in Very Long Instruction Word (VLIW) processors, it is not always used due to low application's Instruction Level Parallelism (ILP). Approaches benefit the additional resources to provide fault tolerance. When permanent and soft errors coexist, spare units have to be...
The Network Function Virtualization (NFV) paradigm promises to make networks more scalable and flexible by decoupling the network functions (NFs) from dedicated and vendor-specific hardware. However, network and compute intensive NFs may be difficult to virtualize without performance degradation. In this context, Field-Programmable Gate Arrays (FPGAs) have been shown to be a good option for hardware...
Reliability is one of the most critical factors that is to be considered during the designing phase of any product. There are many factors that contribute to make a system more reliable in terms of area, power, operating frequency and accuracy. This paper proposes the design of a 4bit fault tolerant ALU system using backend designing. Parallel processing along with triple modular redundancy (TMR)...
Dynamic Partial Reconfiguration is an important feature of modern FPGAs as it allows for better exploitation of FPGA resources over time and space. The Internal Configuration Access Port (ICAP) enables DPR from within an FPGA chip, leading to the possibility of fully autonomous FPGA-based systems. This paper presents a novel high performance and fault-tolerant ICAP controller which can operate at...
The continuous requirement to provide safe, low-cost, compact systems makes applications such as automotive more prone to increasing types of faults. This may result in increased system failure rates if not addressed correctly. While some of the faults are not permanent in nature, they can lead to malfunctioning in complex circuits and/or software systems. Moreover, automotive applications have recently...
High reliability is usually the most important requirement in space applications. There is no hardware repair for them. Long mission times and harsh environment are a challenge for electronic circuits, and particular error mitigation techniques have to be implemented in order to be able to cope with the expected error effects. Always, Triple Modular Redundancy (TMR) is relied mostly to prevent SEUs...
Commercial graphics processing units (GPUs) prove their attractive, inexpensive in high performance scientific applications. However, a recent research through Folding@home demonstrates that two-thirds of tested GPUs on Folding@home exhibit a detectable, pattern-sensitive rate of memory soft errors for GPGPU. Fault tolerance has been viewed as critical to the effective use of these GPUs. In this paper,...
Circuits implementing the concept of Selective Fault Tolerance according to are fault-tolerant for a specified subset of inputs. In this paper, a new heuristic is presented to make the method of Selective Fault Tolerance applicable to industrial designs. The heuristic can be efficiently implemented by use of conventional design tools. Compared to TMR, the method, in combination with the heuristic,...
This paper proposes a novel methodology for improving reliability of FPGAs without requiring special purpose hardware. In contrast to related approaches that are applied uniformly over the target architecture, the proposed one insert redundancy only the critical for failure resources. Such an approach leads to reasonable performance improvement.
In this paper a design diversity fault tolerance technique is applied to a mixed-signal (MS) system. Three different implementations of a second order low-pass filter (which perform the same transfer function) associated to a majority voter are used to build the TMR scheme. The whole system is prototyped by using a programmable mixed-signal device. Some functional faults are injected into the circuit...
The growing demand for secure communications has lead to the utilization of cryptographic mechanisms on-board spacecrafts. However, that it not a trivial task due to sensitivity of cryptographic primitives to bit-flips, which are commonly caused by the radiation found in space. On-board processing has mitigated single event upsets (SEUs) by employing the traditional triple modular redundancy (TMR),...
This paper presents a PCI-Express based platform for the analysis and evaluation of designs that combines Triple Modular Redundancy and Dynamic Reconfiguration to provide Fault Tolerance and Self-repairing capabilities. The paper presents the general architecture of the platform and exemplifies its functionality with the implementation of a Self-Repairing CAN Gateway.
This article presents a precise synchronization algorithm based on status tracking and locking mechanism. Tracking execution state of triple computer and running state of time base counter through dual state machine not only can implement precise synchronization of TMR computer, making status synchronization precision and time-base synchronization precision below 30ns, but also save valuable interconnection...
Onboard Reconfigurable Processing Platform (ORPP), which mainly consists of reconfigurable devices (FPGAs) and auxiliary co-processors such as DSPs, is dedicated to in-situ real-time computing for various space missions. Harsh ionizing radiation effects have been observed during flight thus make it crucial to design fault tolerance in ORPPs. Transient available refers to ORPP can mask transient faults...
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