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Network-on-Chip (NoC) is an interesting communication fabric for multi processing element architectures that benefits from the parallelism of algorithms. We present a method that uses a symbolic execution technique to extract the parallelism of an application to be mapped on FPGAs using the flexibility of a NoC communication infrastructure and the properties of a high level programming language. An...
In order to convert High Level Language (HLL) into hardware, a Control Dataflow Graph (CDFG) is a fundamental element to be used. Otherwise, Dataflow Architecture, can be obtained directly from the CDFG. In the 1970s and late 1980s, the Dataflow Model was the focus of attention that provided parallelism in a natural form. In particular, dynamic dataflow architecture can be generated to produce a high...
Both performance and energy efficiency are critical concerns for embedded systems and portable devices. Multi-issue processors can exploit the instruction-level parallelism (ILP) of programs to improve the performance greatly, however, most of the time at a cost of energy and power consumption. How to reduce the energy consumption while maintaining the high performance of programs running on multi-issue...
The main challenge in designing a mobile wireless software defined radio (SDR) system is to provide a solution that has high flexibility, hardware-like throughput, low power consumption, in addition to ease of programmability. In this paper, the authors propose a new architecture for SDR that is based on a reconfigurable instruction cell array (RICA). The architecture targets the IEEE 802.11g standard...
Clock acceleration and ILP extraction have drastically improved processor performance. However, the performance of memory has not improved as much as that of processors, thus the problem of performance gap between memory and processor, which is called the memory wall problem, is becoming very serious. This will become more serious in the near future. We propose a new VLSI architecture which can solve...
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