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The effect of process variability on power and performance of integrated circuits can only be reduced with statistical optimization techniques. In this paper, we examine optimum VDD-VT design for minimizing power in deep-submicron CMOS circuits and introduce highly-efficient algorithm for yield constrained optimum power operation to include the impact of process variability and avoid the limitations...
There are several techniques available to control the leakage current in deep sub-micron technologies. One of the techniques is the Input Vector Control (IVC). By using IVC, leakage power consumption of a circuit can be minimized in the off state. In this paper, an algorithm has been given to calculate the best input vector that can be applied to the circuit (designed with 65nm technology transistors)...
In this paper, we focus on the placement of cells in a CMOL array given a specific connectivity domain using the Ant Colony Optimization algorithm. We describe the algorithm and using example circuit show that our approach provides a better placement than other recent work in terms of the number of buffers needed.
Due to the significance of leakage power for CMOS circuits at Nanoscale, a new technique for Sub-threshold leakage current reduction based on Input vector control (IVC) is proposed. The proposed algorithm is called Fast Input Vector Algorithm (FIVA). It is characterized as faster than other algorithms, its speed doubles strongly of other algorithms speed when the number of circuit inputs increases...
Neuromorphic computing is an attractive avenue of research for processing and learning complex real-world data. With technology migration into nano and molecular scales several area and power efficient approaches to the design and implementation of artificial neural networks have been proposed. The discovery of the memristor has further enabled the realization of denser nanoscale logic and memory...
Aggressive scaling of CMOS technology has enabled faster and smaller designs but has posed new challenges. In the deep-submicron era, leakage power has become a major contributor to the overall power dissipation of an IC. In this paper, we present a weighted partial Max-SAT (WPMax-SAT) based approach to find the minimum leakage vector (MLV) of a combinational design. In its exact form, this technique...
We propose a built-in scheme for generating all patterns of a given deterministic test set T. The scheme is based on grouping the columns of T, so that in each group of columns the number ri of unique representatives (row subvectors) as well as their product R over all such groups is kept at a minimum. The representatives of each group (segment) are then generated by a small finite state machine (FSM)...
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