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Electromigration of flip-chip solder joints has been studied extensively in recent years. It was investigated in plenty of studies that the current crowding effect takes place at the corner near the traces due to huge differences of dimensions between traces and solder joint. The local high current density, which has been known as a serious reliability issue, causes the failure such as void formation...
Die size effects on chip package interaction for Cu/ultra low-k interconnect in flip chip package were investigated using mechanical and thermal analysis. The analytical and the theoretical study suggested that the die size effects were not caused only by the mismatch in CTE between die and substrate. By considering the number of bonding solder and its mechanical property during the cooling process,...
The study of low-k TDDB line space scaling is important for assuring robust reliability for new technologies. Although spacing effects due to line edge roughness (LER) on low-k TDDB lifetime were reported previously (Chen et al., 2007; Lloyd et al., 2007; Kim et al., 2007), there has been a lack of an analytical model with which to link line edge roughness to experimental TDDB data in a simple quantitative...
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