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In this paper, we propose models for single and coupled on-chip global interconnect lines by distributed RLGC parameters using state space approach. Models for single and coupled lines are validated by comparing with SPICE simulations. Interconnect performance metrics are obtained from the proposed models for 65 nm, 90 nm, 130 nm and 180 nm technology nodes based on PTM values. In case of coupled...
A new model for calculating capacitive and resistive coupling is developed in this work and its implementation in commonly encountered practical cases is presented. The model is based on the geometry of the coupling mechanism and is therefore, in general, scalable and technology independent, while pure 3D effects, like capacitive coupling, are fast and accurately computed. The proposed model is validated...
Back-end-of-the-line (BEOL) interconnect becomes a limiting factor to circuit performance in scaled complementary metal-oxide-semiconductor design. To accurately extract its paratactic capacitance for circuit simulation, compact models should be scalable with wire geometries and should capture the latest technology advances, such as the air gap and Cu diffusion barrier. This paper achieves these goals...
As double patterning technology (DPT) becomes the only solution for 32-nm lithography process, we need to investigate how DPT affects the performance of a chip. In this paper, we present an efficient modeling of timing variation with overlay which is inevitable for DPT. Our work makes it possible to analyze timing with overlay variables. Since the variation of metal space caused by overlay results...
A novel methodology for accurate and efficient static timing analysis is presented in this paper. The methodology is based on finding a frequency domain model for the gates which allows uniform treatment of the gates and interconnects. It is shown that despite the highly nonlinear overall gate model, a frequency domain model of the gate with the model parameters, gate moments, as functions of the...
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