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Due to their out-standing performance (huge bandwidth and high signal quality), optical communications have become the standardized technologies suited for long reach and high bit-rate communication systems. Nevertheless, the traditional incompatibility of CMOS with the optical technology, and the difficulty for all-optical implementation of some key functions such as buffering and header processing,...
Future processors are expected to be made up of a large number of computation cores interconnected by fast on-chip networks (Network-on-Chip, NoC). Such distributed structures motivate the use of message passing programming models similar to MPI. Since the properties of these networks, like e.g. the topology, are known and fixed after production, this knowledge can be used to optimize the communication...
Network-on-Chip (NoC) is believed to be a solution to the existing and future interconnection problems in highly complex chips. Different alternatives proposed circuit-switched NoCs to guarantee performance and Quality-of-Service (QoS) parameters for Systems-on-Chips (SoC). However, implementing scheduling mechanisms with different service classes and exploring the advantages of wormhole routing and...
Three Dimensional Integrated Circuits (3D ICs) are emerging to improve existing Two Dimensional (2D) designs by providing smaller chip areas, higher performance and lower power consumption. Stacking memory layers on top of a multiprocessor layer (logic layer) is a potential solution to reduce wire delay and increase the bandwidth. To fully employ this capability, an efficient on-chip communication...
Networks-on-Chip (NoCs for short) are known as the most scalable and reliable on-chip communication architectures for multi-core SoCs with tens to hundreds IP cores. Proper mapping the IP cores on NoC tiles (or assigning threads to cores in chip multiprocessors) can reduce end-to-end delay and energy consumption. While almost all previous works on mapping consider higher priority for the application's...
This paper presents a novel application mapping strategy onto the Butterfly Fat Tree (BFT) topology for Network-on-Chip (NoC) design. It proposes a Kernighan-Lin bi-partitioning strategy to identify the closeness of cores by analyzing their bandwidth requirements. The nodes are then mapped to the BFT topology. The BFT mapping results have been compared with mesh-mapping results reported in the literature...
In this paper, we propose a processor allocation mechanism for run-time assignment of a set of communicating tasks of input applications onto the processing nodes of a Chip Multiprocessor (CMP), when the arrival order and execution lifetime of the input applications are not known a priori. This mechanism targets the on-chip communication and aims to reduce the power and latency of the NoC employed...
3D technologies using Through Silicon Vias (TSV) have not yet proved their viability for being deployed in large-range products. In this paper, we investigate three promising perspectives for short to medium terms adoption of such technology in high-end System-on-Chip built around multi-core architectures: the wide bus concept will help solving high bandwidth requirements with external memory. 3D...
A bidirectional channel network-on-chip (BiNoC) architecture is proposed to enhance the performance of on-chip communication. In a BiNoC, each communication channel allows to be dynamically self-reconfigured to transmit flits in either direction. This added flexibility promises better bandwidth utilization, lower packet delivery latency, and higher packet consumption rate. Novel on-chip router architecture...
This paper presents a novel application mapping strategy onto the mesh topology for Network-on-Chip (NoC) design. Compared to the previously published works, this paper uses the approach of Kernighan-Lin bi-partitioning strategy to identify the closeness of cores by analyzing their bandwidth requirements. The nodes are then mapped to the topology using another heuristic algorithm. An iterative improvement...
A virtual channel (VC) calculation algorithm for wormhole-switched on-chip networks is proposed. Traditionally, the virtual channels were allocated uniformly, which results in a waste of area and power. To remedy this situation, based on the queuing theory, we propose a router analytical model. Using this model, the proposed algorithm calculates the bandwidth usage at each router in the network according...
This paper present a new dimension-oriented routing algorithm for Mesh-of-tree (MoT) based Network-on-Chip (NoC) architecture. The addressing scheme is considerably simplified that enables us to reduce the minimum flit-size to 16-bits, compared to 32-bits in the previously reported works. The same level of throughput and average latency could be achieved with a 43.86% reduction in area and 43% reduction...
Application-specific SoC requires an efficient interconnection topology which does not necessarily conform to regular topologies such as mesh etc. As NoC topology synthesis is an NP-hard problem, we present a genetic-algorithm (GA) based technique to synthesize application-specific NoC topology with system-level floorplan aware. The technique minimizes the power consumption and router resources while...
Several alternatives of mesh-type topologies have been published for the use in Networks-on-Chip. Due to their regularity, mesh-type topologies often serve as a foundation to investigate new ideas or to customize the topology to application-specific needs. This paper analyzes existing mesh-type topologies and compares their characteristics in terms of communication and implementation costs. Furthermore,...
Periodic on-chip scan-based tests have to be applied to a many-core processor SoC to improve its dependability. An infrastructural IP module has been designed and incorporated into the SoC to function as an ATE. This paper introduces the reuse of a Network-on-Chip as a test access mechanism. Since the scan-based test is performed on-chip via the NoC at application run-time, it needs to share the NoC...
In this paper we present a scalable wormhole switch architecture with a credit based guaranteed service implementation. By means of credits for a service guarantee the architecture is also able to deal with mesochronous GALS systems. We extended a regular wormhole switch architecture with a control unit for service configuration during run-time and modified the arbitration policy. These changes result...
As chip multiprocessors transition from multi-core to many-core, on-chip network power is increasingly becoming a key barrier to scalability. Studies have shown that on-chip networks can consume up to 36% of the total chip power, while analysis of network traffic reveals that for extended periods of execution time, network load is well below the network capacity in many applications. In recent studies,...
In this paper, we propose a hybrid method to provide Quality of Service (QoS) for Networks-on-Chip (NoC). This method combines the advantages of connection-based schemes and connection-less schemes. Thus, compared with traditional methods, this method guarantees the latency between one flit's generation in the source node and its reception in the destination node, supports a wide range of traffic...
Inter-Processor communication synchronization in multi-processor system-on-chip (MPSoC) is one of the key factors for the whole chip performance. It cannot only affect the efficiency of task-level parallelism, but also has high dependency on MPSoC hardware architecture. Two synchronization mechanisms, i.e. mailbox and packet switching, are studied and analyzed in Network on chip based MPSoC. At first,...
Network on Chip (NoC) is considered as the promising diagram of interconnection mechanism for future chip multiprocessors. As the number of processing elements (PE) on chip keeps growing, the delay for simultaneous memory references of these PEs is emerging as a serious bottleneck on high performance. One major part of this delay is from the Memory Management Unit (MMU) due to its centralized structure...
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