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A power-efficient frequency compensation topology, Impedance Adapting Compensation (IAC), is presented in this paper. This IAC topology has, on one hand, a normal Miller capacitor, which is still needed to provide an internal negative feedback loop, and on the other hand, a serial RC impedance as a load to the intermediate stage, improving performance parameters such as stability, gain-bandwidth product...
The application of current sense amplifiers in scaled SRAM design is limited by two factors: the DC offset due to the device mismatch and limited voltage headroom. The presented scheme reduces the effect of offset by proposing an extra phase for offset cancellation before current sensing takes place. A twofold reduction of the cell access time is achieved compared to the conventional scheme under...
A high-temperature amplifier, designed and simulated in a 0.13 mum CMOS process, is presented. The amplifier is intended to operate in a wood chip digester used for pulp manufacture in which the ambient temperature can be as high as 180degC. Since the foundry provided modeled are valid up to 125degC, the amplifier along with its bias circuitry is simulated up to 125degC by considering a reasonable...
This paper presents a wide-swing source follower with resistive load capability designed in TSMC 0.18 mum CMOS technology. Two additional amplifiers are employed to enlarge its input swing. The resultant stability problem is solved by a simple compensation scheme based on analysis of the system transfer function. Under a 1.8V supply the source follower, when loaded by a 1KOmega resistor and shifting...
This paper introduces a novel current sense amplifier (CSA) in sub-32nm fully depleted (FD) double-gate (DG) silicon-on-insulator (SOI) technology with planar independent self-aligned gates. A new architecture is proposed which takes advantage of the back gate in order to improve circuit properties. Compared to the reference circuit, the new architecture proves to be faster (21% sensing delay decrease),...
A novel SRAM architecture with a high density cell in low supply voltage operation is proposed. A self-write-back sense amplifier realizes cell failure rate improvement by more than two orders of magnitude at 0.6 V. A cascaded bit line scheme saves additional process cost for hierarchical bit line layer. A test chip with 256 kb SRAM utilizing 0.495 um2 cell in 65 nm CMOS technology demonstrated 0...
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