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This paper presents a temperature and supply compensated sub-threshold voltage reference generator which generates a reference voltage of 173 mV at supply voltage of 0.6 V and temperature @ 27 °C, has been designed in 45 nm CMOS technology. Variation of output voltage with temperature over a range of −25 to 85 °C is 172.88 to 173.25 mV which gives temperature coefficient of 19 ppm/°C at supply voltage...
A modulo 2n−2 value has been proposed in Residue Number System (RNS)-based systems for the design of FIR filters and communication components. However, all modulo 2n−2 arithmetic units that were used have been based either on look-up tables or on generic modulo arithmetic structures. In this work we propose novel modulo 2n−2 adder, multiplier as well as residue generation architectures that take advantage...
This paper explains the creation of new approach of propagation delay measurement in nanostructures during characterization of ASIC standard library cell. Providing more accuracy timing information about library cell (NOR, AND, XOR, etc.) to the design team we can improve a quality of timing analysis inside of ASIC design flow process. Also, this information could be very useful for semiconductor...
In this paper we present an overview of design implementation of a Symmetrical Multiple Valued Logic (SMVL) arithmetic circuit based on the use of restricted moduli Symmetrical Signed Residue Number System (SSRNS). Restricted radix-7 Symmetrical quaternary Signed digit (Rr7SqSd) T-gate based interconnections and full adders are used to implement sign detection, overflow detection and magnitude comparison...
Scan testing and scan compression have become key components for reducing test cost, and most high-compression schemes are based on linear, sequential compressors e.g., pseudo-random pattern generators (PRPG). We present a novel technique to increase PRPG-based compression by modifying test generation so that justification of certain decision nodes is delayed and merged with PRPG seed computation...
Color codes are a class of topological codes that have come into prominence in the recent years. Like the surface codes the codespace defined by them can be associated to the degenerate ground state of a local Hamiltonian. In addition they can be designed to have an extended set of transversal encoded gates (compared to surface codes) increasing their appeal for fault tolerant quantum computation...
Cauchy Reed/Solomon is an XOR-based erasure-tolerant coding scheme, applied for reliable distributed storage, fault-tolerant memory and reconstruction of content from widely distributed data. The encoding and decoding is based on XOR operations and already well supported by microprocessors.On multicore processors, the coding procedures should also exploit parallelism to speed up coding. In this paper...
Arithmetic bit-level (ABL) normalization has been proven a viable approach to formal property checking of datapath designs. It is applicable where arithmetic components and sub-components can be identified at the register-transfer (RT) level of the design and the property. This paper extends the applicability of ABL normalization to cases where some of the arithmetic components are custom-designed...
Error correction is an effective way to mitigate fault attacks in cryptographic hardware. It is also an effective solution to soft errors in deep sub-micron technologies. To this end, we present a systematic method for designing single error correcting (SEC) and double error detecting (DED) finite field (Galoisfield) multipliers over GF(2m). The detection and correction are done on-line. We use multiple...
This paper solves the problem of minimizing triple bit error miscorrection for single-error-correcting, double-error-detecting codes (SEC-DED codes) which are used to protect all kinds of memory against errors. A lower bound for triple bit error miscorrection for the widely used class of odd-weight column codes is derived and actual codes which are very close to that theoretical bound are presented...
A delay-locked loop of multi-band selector with wide-locking range and low power dissipation is presented. The architecture of the proposed delay-locked loop consists of phase frequency detector, charge pump, band selector, multi-control delay line, and start-up circuit. The multi-band selector is used to extend operation frequency of delay-locked loop by switching the multi-control delay line. The...
Based on simple comparison between a conventional navigation receiver and a GNSS software receiver, a generic GNSS receiver architecture is given, which focuses on the GPS IF signal processing algorithm in the channel. According to the channel states the algorithm falls into four parts: signal acquisition, confirmation, fine frequency estimation and tracking. A frequency domain acquisition based on...
Li and Xia have recently investigated the design of space-time codes that achieve full spatial diversity for asynchronous cooperative communications. They show that certain of the binary space-time trellis codes derived from the Hammons-El Gamal stacking construction are delay tolerant and can be used in the multilevel code constructions by Lu and Kumar to produce delay tolerant space-time codes for...
Orthogonal frequency division multiplexing (OFDM) is the modulation scheme of choice for digital video broadcasting-handheld (DVB-H), which is required to operate under high mobility conditions resulting in significant Inter-carrier Interference (ICI). To mitigate ICI, several cancellation schemes have been proposed but they require reliable channel information at the receiver which is quite challenging...
We designed and built a novel all-optical re-timing, re-amplifying, and re-shaping (3R) regeneration system based on terahertz optical asymmetric demultiplexers (TOADs) developed in our laboratory. The system is capable of parallel processing multiple wavelengths, a feature which will significantly improve the scalability of current wavelength division multiplexing (WDM) networks. Performance against...
A charge-control model of the BMFET, based on a physical analysis of its operation is presented and discussed. This model is used to derive an equivalent circuit of BMFET capable of describing, with continuity, both bipolar and unipolar regions of its characteristics. The equivalent circuit is presented in a form suitable to be easily incorporated in a circuit simulator such as SPICE.
This paper presents an extremely efficient, non-interactive protocol for verifiable secret sharing. Verifiable secret sharing (VSS) is a way of bequeathing information to a set of processors such that a quorum of processors is needed to access the information. VSS is a fundamental tool of cryptography and distributed computing. Seemingly difficult problems such as secret bidding, fair voting, leader...
The notion of a zero knowledge interactive proof that one party "knows" some secret information is explored. It is shown that any "random self-reducible" problem has a zero knowledge interactive proof of this sort. The zero knowledge interactive proofs for graph isomorphism, quadratic residuosity, and "knowledge" of discrete logarithms all follow as special cases. Based...
We show that the permutation group membership problem can be solved in depth (logn)3 on a Monte Carlo Boolean circuit of polynomial size in the restricted case in which the group is abelian. We also show that this restricted problem is NC1-hard for NSPACE(logn).
A design tool for the decomposition of binary digital structures for addition and subtraction has been developed. A simplified theory reduces a complex structure to a collection of basic structures of one type, namely, a full adder. The simplified theory is applicable to the design of parallel counters and array multipliers. A general theory is used for decomposition to three types of basic structures,...
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