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Field Programmable Gate Arrays (FPGAs) used in mission-critical applications such as aerospace, nuclear, and defense require high reliability in spite of internal faults. Fortunately, today's FPGAs have the ability to dynamically reconfigure themselves in the field, which may help to mitigate the effects of certain faults affecting the FPGA devices. Although the reconfiguration process can remove...
Soft processors have been commonly used in FPGAbased designs to perform various useful functions. Some of these functions are not performance-critical and required to be implemented using very few FPGA resources. For such cases, it is desired to reduce circuit area of the soft processor as much as possible. This paper proposes Ultrasmall, a small soft processor for FPGAs. Ultrasmall supports a subset...
Point Multiplication (PM) is considered the most computationally complex and resource hungry Elliptic Curve Cryptography (ECC) related mathematic operation. The design of PM hardware accelerators follows approaches that have a trade off between utilized hardware resources and computation speed. In this paper, the above trade-off and its relation with the operations of the GF(2k) defining the Elliptic...
This paper presents a dynamically configurable and area-efficient multi-precision architecture for Floating Point (FP) division. FP division is a core arithmetic in scientific and engineering domain. We propose an architecture for double precision (DP) division which is also capable of processing dual (two-parallel) single precision (SP) computation, named as DPdSP FP divider. The architecture is...
Hardware binding is a crucial step in high-level synthesis. In this paper we propose a path based hardware binding algorithm to create area-time efficient designs. The algorithm performs simultaneous FU and register binding based on weighted and ordered compatibility graphs. The proposed algorithm tries to reduce interconnects in the design by exploiting flow dependencies in the DFG, leading to area...
Demand for decimal floating-point (DFP) arithmetic is growing. Yet most processors do not include hardware DFP support, and must instead use slow software DFP libraries. FPGAs are a potential solution to add hardware-based high-performance, parallel DFP engines to existing compute clusters without completely replacing those systems. This paper describes the FPGA implementation of a 64-bit DFP adder...
In this paper we propose and evaluate our platform to accelerate applications using custom instruction set extensions. We use a dynamically reconfigurable functional unit (DRFU) to execute the application specific custom instructions generated by our compiler framework. We explore two architectures with different computational granularities for the DRFU (look-up table and ALU based) and evaluate this...
Reconfigurable computing has been driven largely by the development of commodity field-programmable gate arrays (FPGAs). Standard FPGAs are somewhat of a mixed blessing for this field.In this survey we give a brief overview of programming logics and we present configurable logic block (CLB) and look up table (LUT) as logic elements. Also we presented the definition of fine and coarse-grain architectures...
Inspired by the idea of hardware time division multiplexing(TDM), a multi-channel digital down converter (DDC) is devised by exploring maximum resource reuse, which is realized by sharing memory, adders and multipliers among several independent channels, so that the resource cost is reduced significantly. Finally, a design example is implemented with FPGA, and simulations verify its feasibility.
This paper presents a non-monolithic top-down reconfigurable multiplier suitable for embedding in an FPGA structure. It is constructed of four individual partitions that can operate as separate multipliers but also concatenate to form a superior multiplier with increased precision and sign handling ability. The number of possible operation modes is limited in order to keep the reconfiguration overhead...
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