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This paper presents an efficient VLSI architecture for the implementation of Motion Estimation (ME) for real-time video processing using New Three Step Search Algorithm (NTSS). The proposed architecture employs sequential processing of pixels with a view to reduce the hardware complexity and achieve real-time speed requirement simultaneously. A novel memory addressing scheme has been proposed which...
Motion estimation plays an important role in inter-frame prediction for the video coding standards such as H.264/AVC, MPEG-2, MPEG-4, VC-1, and so on. Its huge computation complexity, however, makes it difficult to achieve real-time coding for the HDTV1080p. In this paper, we propose a dynamic search range algorithm which reduces about 80% of search points in full search algorithm for the H.264/AVC...
Bidirectional motion estimation is an efficient algorithm which can solve the problem of holed and overlapped regions for motion compensated frame interpolation in frame rate up-conversion applications. This paper proposed an efficient VLSI architecture for this algorithm using multi-resolution frames to reduce the hardware resource. The initial motion vectors (MVs) in bidirectional motion estimation...
Variable block size motion estimation (VBSME) is becoming the new coding technique in H.264/AVC. This paper presents a low-power VLSI implementation for full-search VBSME. Compared to existing hardware architectures and implementations for VBSME, the proposed design employs a fast full-search block matching algorithm to reduce power consumption, while preserving the optimal solution and the throughput...
In AVS video coding standard, some algorithms consume huge computation with relatively little coding performance contribution, and some algorithms create data dependencies that are harmful for efficient hardware pipeline. This paper focuses on hardware oriented algorithm analysis and modification. Motion estimation and mode decision algorithms are reviewed and modified to a hardware friendly configuration...
Variable block size (VBS) transform technique is adopted in Fidelity Range Extensions (FRExt) of H.264/AVC, in which 8 ?? 8/4 ?? 4 Hadamard transforms are adaptively employed during the fractional motion estimation. The hardwired VBS Hadamard transform unit is developed by authors and the following contributions are described in this literature: (1) Hardware reusing scheme is adopted in the architecture...
Motion estimation is the most computationally demanding task in MPEG-4 based video compression techniques. Motion estimation consumes 70% of the computational capability and its hardware realization contributes up to 60% of chip power. This paper describes our efforts in analyzing power consumption of motion estimation in custom VLSI architecture prototyped as a configurable system on a chip (CSoC)...
This paper proposes a parallel architecture for fast two-step search algorithm, which is used in sub-pixel motion estimation with reduced complexity. As frequent data access is necessary to execute the algorithm which involves interpolation, an architecture efficient in terms of the memory bandwidth is suitable for implementing the algorithm. In the present paper, an architecture based on an intelligent...
The latest H.264/AVC standard can provide us superior coding performance. However, the new technique also brings about complexity problem, especially in motion estimation (ME) part. In hardware, the pipeline stage division of H.264 based ME engine degrades many software oriented complexity reduction schemes. In our paper, we propose one VLSI friendly fast ME algorithm. Firstly, pixel difference based...
A H.264/AVC baseline-profile real-time encoder for HDTV-1080p at 30 fps is proposed in this paper. On the basis of the specifications and algorithm optimizations, the dedicated hardware engines and one 32-bit media embedded processor (MeP) equipped with hardware extensions are mapped into the three-stage macroblock pipelining system architecture. This paper describes the design considerations for...
In this paper, two hardware-oriented fast motion estimation algorithms and their implementations into a 2D systolic array for variable block size motion estimation architecture are presented. Two hardware oriented algorithms are proposed to increase the coding speed and reduce the computation complexity of the fast motion estimation (FME) algorithm. The results show that the proposed FME algorithm...
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