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Accurate hold time analysis of sequential cells is crucial to high performance enterprise server microprocessor circuit design. Due to tight timing margins, process variation, and increased instance counts of latches and flops in a microprocessor, fast and accurate hold time analysis with process variation consideration is needed. In this article, we present a novel, high-sigma, SPICE-based analysis...
The heat diffusion model of IC chip is equivalent to electrical resistors and capacitors (RC) network. Instead of using direct methods to solve the network equations, a novel statistical method based on random walk techniques was proposed for thermal RC network analysis in this paper. The corresponding 2 dimension temperature distribution was derived finally. Experimental results show the simulation...
Modeling process variations in circuits is becoming necessary as the technology continues to shrink in size. When this is coupled with increasing frequencies of operation of circuits in communication systems (>10 GHz), the use of full-wave field solvers is necessary to model the on-chip passive components such as spiral inductors and transformers. Thus it becomes necessary to couple full-wave field...
This paper studies the impact of intra-die random variability on low-power digital circuit designs, specifically, circuit timing failures due to intra-die variability. We identify a new low-Vdd statistical failure mode that is strongly supply-voltage dependent and also introduce a simple yet novel method for quantifying the effects of process variability on digital timing - a delay overlapping stage...
We present a generic method for analyzing the effect of process variability in nanoscale circuits. The proposed framework uses kernel and a generic tail probability estimator to eliminate the need for a-priori density choice for the nature of circuit variation. This allows capturing the true nature of the circuit variation from a few random samples of its observed responses. The data-driven, non-parametric,...
The dramatic increase in leakage current, coupled with the swell in process variability in nano-scaled CMOS technologies, has become a major issue for future IC design. Moreover, due to the spread of leakage power values, leakage variability cannot be neglected anymore. In this work an accurate analytic estimation and modeling methodology has been developed for logic gates leakage under statistical...
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