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A low-voltage 5th-order continuous-time ΣΔ modulator for a universal mobile TV receiver is presented. A unique feature of the proposed modulator is the blocker filtering provided using a 3rd order notch filter employing frequency dependent negative resistance (FDNR). The noise added by the FDNR is shaped. The modulator employs 3-level switched-capacitor DAC in the feedback. It has been implemented...
We present a CT-DeltaSigma modulator operating at a sampling rate of 300 Msps in a 0.18 mum CMOS process. A low power four bit flash ADC and a complementary current-steering DAC are used to reduce power and noise. The opamps used in the active-RC loop filter are deliberately made slow to further reduce current consumption and the resulting loop delay is compensated. The modulator achieves a peak SNR...
This paper describes a comparative analysis between two topologies of operational amplifiers to design a 40 MS/s 12-bit pipeline analog to digital converter (ADC). The analysis includes AC and transient simulation to select the proper topology. This ADC is implemented in a 0.35 mum AMS CMOS technology with 3.3 V single power supply. The capacitors and selected operational amplifiers were scaled for...
A high intercept points, cost-effective, and power-efficient switching FET double balanced mixer (DBM) is reported. The Switching FET DBM demonstrated in this work offers input intercept points (IIP3) and conversion loss typically 44 dBm and 8.5 dB respectively with 15 dBm LO power for the frequency band (RF: 900-2150 MHz, LO: 850-1950 MHz, IF: 50-200 MHz). The measured interport isolation is typically...
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