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This paper presents the implementation of Successive Approximation Architecture (SAR) based Analog to Digital Convertors (ADC). In order to reduce the power consumption and increase the speed, a double-tail latch type comparator is incorporated in the design. Charge redistribution DAC is used for area efficiency. A synchronous type SAR Logic with counter based controlled unit is proposed for faster...
This paper presents a novel, fully-integrated circuit for achieving change-balanced voltage-mode neural stimulation based on a charge-metering technique. The proposed system uses two small on-chip capacitors, a counter, two comparators and a control-logic circuit to measure the charge delivered to the tissue. This has been designed to deliver a maximum charge stimulus of 10.24 nC within 100 µs. Simulated...
A delay-locked loop of multi-band selector with wide-locking range and low power dissipation is presented. The architecture of the proposed delay-locked loop consists of phase frequency detector, charge pump, band selector, multi-control delay line, and start-up circuit. The multi-band selector is used to extend operation frequency of delay-locked loop by switching the multi-control delay line. The...
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