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Hardware realization of fast Fourier transform (FFT) function consists of multiple complex arithmetic operations. Floating point implementation of FFT provides wider dynamic range than their fixed point counterparts and fusing the floating point arithmetic operations inside the Butterfly unit of FFT improves the speed of operation. This paper presents an FFT implementation using a fused four term...
Performance of adders has a tremendous impact on system-level functionality especially in signal processing applications. Carry Select Adder (CSLA) is one such adder which is proved to be a high speed version among other conventional adders. This paper presents a novel architecture for SQRT-CSLA with modified ripple carry adder chain. The pivotal feature of the proposed architecture is that the final-sum...
The image processing applications require low power and high speed, the convolution based 1D-DWT is not desirable. In this proposed architecture the modified 5/3 lifting algorithm is realized on FPGA platform with optimizations. The latency and throughput is optimized with the modified algorithm. The architecture is modelled using HDL and implemented on FPGA. The proposal operates at 178MHz and realised...
The paper presents the design of a MAC unit that is based on the Vedic Square and its application, for the processing of equations that solely contain square terms. The use of Vedic Square as a replacement of the multiplier helps in reduction of area. In this paper, the Vedic Square is compared to the Vedic multiplier; both are based on the UrdhvaTiryagbhya sutra of Vedic mathematics. Duplex property...
Wallace tree multipliers provide a power-efficient strategy for high speed multiplication. The use of high speed 7∶3 counters in the Wallace tree reduction can further improve the multiplier speed. This paper presents an algorithmic approach to construct the counter based Wallace tree multipliers. The proposed algorithm can be used to implement the efficient counter based Wallace multiplier of any...
Multiplication is one of the most commonly used operations in the signal processing algorithms. Multipliers based on Wallace reduction tree provide an area-efficient strategy for high speed multiplication. A number of modifications are proposed in the literature to optimize the speed and area of the Wallace multiplier. Counter based Wallace multipliers are proved to provide faster operation as compared...
Modulo (231-1) adder is one of the important module in ZUC stream cipher. The paper presents compact, high performance architecture for modulo (231-1) adder using CLA. The proposed architecture is implemented by using VHDL language with CAD tool Xilinx ISE Design Suite 13.2 and target device is Xilinx Spartan3-xc3s1000, with package FG320. Presented result shows that proposed architecture minimizes...
A novel hardware accelerator for the High Efficiency Video Coding (HEVC) intra prediction is presented in this paper in order to reduce the computation complexity within this standard and to accelerate the concerned calculations. We propose a new pipelined structure that we called Processing Element (PE) to execute all angular modes, and we repeat it in five paths that our architecture composed of...
Modular addition and multiplication plays an important role in data encryption standard. In this paper a new VLS I circuit architectures for addition and multiplication of modulo 2n+1 are presented, which allows the implementation of highly efficient combinational circuits for modular arithmetic. The architecture for adder and multipliers are based on Diminished-1 representation. To realize the architecture...
A novel circuit architecture for variable latency adder based on present and transitional states prediction (PTSP) method is presented in this paper, for taking the low power benefits of voltage-over-scaling. With the scaling down of CMOS technology, failure from process variation and high power consumption has become severe problem in VLSI design and the traditional conservative methodology is about...
This paper presents a Reconfigurable Parallel Prefix Ling Adder. The proposed design can be partitioned to perform as one 16 bit, two 8 bit and four 4 bit adders. We also propose a new architecture for Enhanced Flagged Binary Adder (EFBA) designs which reduces the delay of operation considerably. The new adders are, therefore, modifications of conventional Reconfigurable Carry Lookahead Adder (CLA)...
This paper presents fast field programmable gate array (FPGA) analytical dynamic power models for basic operators at the RTL (Register Transfer Level) level. The methodology is an adaptation of an existing incremental power estimation method for Look Up Table based components. The models are based on the frequency, the activity rate and the input precision by using the Xpower tool with a free glitching...
In the latest draft video compression standard, HEVC, a new 8-tap MC interpolation filter is adopted. For this component, we propose an efficient VLSI design which is composed of a reconfigurable filter, an optimized pipeline engine organization, and a filter reuse scheme. This results in 30% area saving from a non-optimized design. The proposed implementation supports a maximal throughput of QFHD@60fps...
This paper reviews a VLSI architecture based on ‘Parallel Pipeline Projection Engine’ (PPPE) which is composed by Forward Radon Transform and Back-projection architecture. This PPPE architecture is modified by using the theory of two-dimensional Radon Transform. The novel architecture is primarily based on analytical relationship between the pixels on horizontal and vertical raster scan line and also...
This paper proposes a novel architecture for high speed combined binary/decimal addition/subtraction. We start by designing a correction-free Binary Coded Decimal (BCD) digit adder which exhibits high performance. We then use the proposed BCD digit adder to create a fast multi-digit BCD adder. The resulting multi-digit BCD adder is then used to build a combined binary/decimal addition/subtraction...
Modeling, simulation and optimization using computing tools are the core approach nowadays in science complementary to experiment and theory. Computational Fluid Dynamics (CFD) has evolved many years ago to simulate fluid physics by solving Navier-Stokes equations, or its simple variants, Euler equations. However, most problems spend many hours to get solutions even with expensive supercomputers or...
The selection of the optimal architecture for a system is done through a process called Design Space Exploration (DSE). This paper presents a novel hybrid exploration process for multi objective modular computing architectures to provide even faster means of architecture selection. The introduced exploration approach radically reduces the number of architectural variants to be analyzed during the...
This paper presents a new design and implementation of a 32-bit decimal floating-point (DFP) antilogarithmic converter based on the digit-recurrence algorithm with selection by rounding. The converter can calculate the accurate antilogarithm (10dec) of the 32-bit DFP numbers which are defined in the IEEE 754-2008 standard. The sequential architecture of the proposed 32-bit DFP antilogarithmic converter...
Since radix-10 arithmetic has been gaining renewed importance over the last few years, high performance decimal systems and techniques are highly demanded. In this paper, a modification of the CORDIC method for decimal arithmetic is proposed so as to improve calculations. The algorithm works with BCD operands and no conversion to binary is needed. A significant reduction in the number of iterations...
In this article, a new design methodology of systolic arrays based on Petri nets is presented. As regards to traditional methods, it takes advantages of using a model very useful in numerous industrial and research applications. After a short reminding on specific properties of basic systolic architectures, the different steps of the method are presented. Architectural Petri nets enable not only the...
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