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In this paper, a cost efficient test methodology to screen chips that have resistive open defects under the presence of process variation is proposed. The proposed test methodology is based on small delay defect testing. The entire test session is divided into several subsessions. In each subsession, test patterns are applied with a different frequency of test clock, all of which are faster than the...
Faster than at-speed testing provides an effective way to detect small delay defects (SDDs). It requires test patterns to be delicately classified into groups according to the delay of sensitized paths. Each group of patterns is applied at certain frequency. In this paper, we propose to generate tests for faster than at-speed testing using path delay fault (PDF) model and single path sensitization...
Today's digital circuits demand both high speed performance and miniaturization of chip size. As a result, delay fault testing has become very important to verify the quality requirements of VLSI chips. Full scan has been used to generate test patterns that achieves high fault coverage, of which the standard techniques for delay scan testing are skewed-load and broad-side. However, as the circuits...
This paper presents SIC based test stimuli with Arithmetic Built in Self-Test (ABIST) concept in order to detect the path delay faults. The presented generator with ABIST stimuli is quite useful for detecting the K-longest path-delay faults of the microprocessor. This paper extends the work of Ø. Gjermundnes and presents its application and validation to the Intel 8051 microprocessor. The experimental...
Test data volume and test application time are major concerns for large industrial circuits. In recent years, many compression techniques have been proposed and evaluated using industrial designs. However, these methods do not target sequence- or timing-dependent failures while compressing the test patterns. Timing-related failures in high-performance integrated circuits are now increasingly dominated...
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