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Timing analysis is a key sign-off step in the design of today's chips, but as technology advances, it becomes ever more challenging to create timing models that accurately reflect real timing-related behavior. Complex dependencies on second order phenomena, such as pattern density and stress/strain make it very difficult to develop device models and simulation tools that accurately predict the timing...
Diagnosis for delay defects becomes more significant as the CMOS process advances to nanometer regime. The most challenging problems of delay fault diagnosis in nanometer process come from the process variation, which results in small delay variations. Small delay variations are difficult to be diagnosed by using existing methods based on a specific fault model. This paper presents a new estimation...
This paper presents a novel approach for identifying non-robustly unsensitizable paths using the bounded delay model for gate delays. A unique feature is that the unsensitizable paths are identified by working on a data structure that stores selected circuit paths instead of the netlist. It is shown that unless the delay of untestable paths are ignored, many non-robust paths will remain undetected...
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