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In this paper, we present a performance comparison of Binary Coded Decimal (BCD) Adders on Field Programmable Gate Logic (FPGA) for functional and behavioural verification. Although it does not prove that the circuit is reversible, implementation on FPGA serves as a platform for functional verification of circuits. BCD adders are one such circuit which has gain wide research emphasis where BCD adders...
Exploiting computational precision can improve performance significantly without losing accuracy in many applications. To enable this, we propose an innovative arithmetic logic unit (ALU) architecture that supports true dynamic precision operations on the fly. The proposed architecture targets both fixed-point and floating-point ALUs, but in this paper we focus mainly on the precision-controlling...
As the size and complexity of embedded systems are growing, the area cost and performance of the LSI circuits are becoming more crucial. A critical bottleneck for them is interconnections such as multiplexers (MUXs). Thus, a hardware synthesis technique for reducing MUXs, especially during the earlier design phase, has been demanded. This paper presents a novel MUX reduction technique in high-level...
This paper is primarily deals the construction of high speed adder circuit using Hardware Description Language (HDL) in the platform Xilinx ISE 9.2i and implement them on Field Programmable Gate Arrays (FPGAs) to analyze the design parameters. The motivation behind this investigation is that an adder is a very basic building block of Arithmetic Logic Unit (ALU) and would be a limiting factor in performance...
Partial reconfiguration technology of programmable devices, such as FPGA, enables the virtualization of hardware circuit by temporal multiplexing of active parts (logic slices). An immediate consequence of virtualization is the increase in cardinality of the don't care set associated with a logic slice. In this paper, we present a logic slicing methodology that exploits the enhanced don't care set...
Various design-for-security (DFS) approaches have been proposed earlier for detection of hardware Trojans, which are malicious insertions in Integrated Circuits (ICs). In this paper, we highlight our major findings in terms of innovative Trojan design that can easily evade existing Trojan detection approaches based on functional testing or side-channel analysis. In particular, we illustrate design...
Hardware Trojans have become a growing concern in the design of secure integrated circuits. In this work, we present a set of novel hardware Trojans aimed at evading detection methods, designed as part of the CSAW Embedded System Challenge 2010. We introduced and implemented unique Trojans based on side-channel analysis that leak the secret key in the reference encryption algorithm. These side-channel-based...
We propose an efficient implementation of Monte Carlo based statistical static timing analysis (MC-SSTA) on FPGAs. MC-SSTA, which repeatedly executes ordinary STA using a set of randomly generated gate delay samples, is widely accepted as an accuracy reference because of its ability to handle any timing distributions and correlations. Extremely long CPU time has been required for the MC-SSTA, which...
Advanced Encryption Standard (AES) is one of the most common symmetric encryption algorithms. The hardware complexity in AES is dominated by AES substitution box (S-box) which is considered as one of the most complicated and costly part of the system because it is the only non-linear structure. The proposed work employs a combinational logic design of S-Box implemented in Virtex II FPGA chip. The...
Malicious alterations of integrated circuits during fabrication in untrusted foundries pose major concern in terms of their reliable and trusted field operation. It is extremely difficult to discover such alterations, also referred to as “hardware Trojans” using conventional structural or functional testing strategies. In this paper, we propose a novel non-invasive, multiple-parameter side-channel...
Previously, a two-step approach to perform the cyclic redundancy check (CRC) computation in hardware was presented. In that approach, an architecture is constructed from a suitable multiple polynomial for a fixed generator polynomial and input size. In this paper, we revisit the two-step approach and suggest a modification to its architecture. First, we propose retiming the second step to the delay...
Decimal multiplication is an integral part of financial, commercial, and internet-based computations. This paper presents a novel double digit decimal multiplication (DDDM) technique that offers low latency and high throughput. This design performs two digit multiplications simultaneously in one clock cycle. Double digit fixed point decimal multipliers for 7digit, 16 digit and 34 digit are simulated...
Fuzzy theory applications have been explored and analyzed on fields as pattern recognition, control, data classification, signal processing, expert systems, among others. To accomplish this, more complex calculations and faster processing speed are required, turning fuzzy hardware implementation to be the perfect choice. Fuzzy operations as t-norms and t-conorms are used in fuzzy systems as conjunction...
Many n-D signal processing applications require realization in real time. We propose the realization of a 3-D spatio-temporal wave digital filter (WDF) in an FPGA. Optimization of the implemented hardware architecture includes evaluation of two different kinds of overflow handling, namely by saturation and a ldquomodulo 2rdquo type operation. The FPGA board is processing DVI signals that can be provided...
The development of a multi-cycle hardware design of a time-varying (TV) filtering system, suitable for real-time implementation on an integrated chip is outlined in this work. Based on results of time-frequency (TF) analysis and the instantaneous frequency (IF) estimation, the proposed design enables multiple detection of the local filter's region of support (FRS) in the observed time-instant, resulting...
Asynchronous design has become more and more popularin last years. Many tools and design methodologies have been developed for this kind of circuits. Unfortunately only few of them are focused on their implementation onto FPGAs. Nowadays FPGAs are widespread in many applications and they have enough complexity to allow prototyping also complex designs. For this reason this paper is focused on the...
MixColumns/InvMixColumns dominates both the logic resource and the critical delay in advanced encryption standard (AES) hardware implementation with direct mapping S-boxes. The proposed decomposition method optimizes the area and the delay of integrated MixColumns/InvMixColumns circuit. Theoretically, the proposed short-path circuit reduces the area up to 42% with the same 5 XOR gates delay (Y.-K...
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