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Mitigation of radiation effects is one of the major problems for space-borne computing platforms. The presented work proposes an approach for building reliable, hardware fault adaptive stream processing platforms for space applications. The proposed concept is based on architecture-to-fault adaptation by run-time hardware reconfiguration. The concept assumes representation of system components in...
Dynamic Partial Reconfiguration (DPR) on FPGAs has attracted significant research interests in recent years since it provides benefits such as reduced area and flexible functionality. However, due to the lack of supporting synthesis tools in current DPR design flow, leveraging these benefits requires specific designer expertise with laborious manual design effort. Considering the complicated concurrency...
Hardware implementations of Internet Protocol (IP) classification algorithms have been proposed by the research community over the years to realize high speed routers and Internet backbone. Decomposition-based IP classification algorithms are desirable for hardware implementation due to their parallel search on multiple fields. These algorithms consist of two phases: independent searches on each packet...
This paper presents a reconfigurable mechanism for the multiplier. The proposed mechanism is applied to generate a multiplier, whose data width, type and pipeline depth can be customized. The data width of each operand of these generated multipliers can be configured for 4i where i=1, 2, 3, 4, 5, 6, 7, 8. And the data type of operand can be unsigned or signed at will. The multiplier is composed of...
IEEE1588 is a Precise Time Protocol (PTP), which is of potentially wide application in control and measurement networks. Stamping PTP messages accurately in physical layer taking advantage of hardware circuits, it is one of important key technologies to achieve the object of high precision time synchronization of IEEE1588. This paper analyzes the content of IEEE1588 standard in detail, and proposes...
Multi-Processor System on Chip (MPSoC) platform plays a vital role in parallel processor architecture design. However, it poses a great challenge to design a flexible high-speed network regarding as the growing number of processors. This paper proposes a star network based on peer to peer links on FPGA. The stat network uses fast simplex links (FSL) for demonstration to connect scheduler and processing...
In this paper, we propose a low-cost sequential and high performance architecture for the implementation of CORDIC algorithm in two computation modes. It suited for serial operation that performs conversion between polar and rectangular coordinate systems, essentially sin/cos, sinh/cosh and arctan computation. In our proposed architecture, radix-2 arithmetic is employed. The design targets real time...
We propose an efficient implementation of Monte Carlo based statistical static timing analysis (MC-SSTA) on FPGAs. MC-SSTA, which repeatedly executes ordinary STA using a set of randomly generated gate delay samples, is widely accepted as an accuracy reference because of its ability to handle any timing distributions and correlations. Extremely long CPU time has been required for the MC-SSTA, which...
Differentiator is widely used to calculate derivative of measured signal in many fields. To improve characteristics of frequency responses, a differentiator using Richardson extrapolation and fractional delay has been proposed. However, to implement fractional delay, some sort of high-order interpolator is needed, which causes many problems. In this paper, to resolve the problems caused by the high-order...
This work is a significant stage of the project, "Digital Arithmetic Public-Key Cryptography". It constructs a modular multiplier for use in the channel of a Residue Number System (RNS). The modular multiplier is implemented on FPGA and optimized by evaluating different versions of the Improved Barrett Algorithm. The resulting optimized multiplier is 12 bits wide and uses separated multiplication...
The importance of processing of digital signals has dramatically increased due to widespread use of digital systems. A new FPGA based technique for processing of two digital signals to generate a new signal as a product of two signals is presented. The technique is based upon the use of orthogonal functions to describe digital signals.
The technique of orthogonal frequency division multiplexing (OFDM) is famous for its robustness against frequency-selective fading channel. This technique has been widely used in many wired and wireless communication systems. In general, the fast Fourier transform (FFT) and inverse FFT (IFFT) operations are used as the modulation/demodulation in the OFDM systems, and the sizes of FFT/IFFT operations...
Advanced Encryption Standard (AES) is one of the most common symmetric encryption algorithms. The hardware complexity in AES is dominated by AES substitution box (S-box) which is considered as one of the most complicated and costly part of the system because it is the only non-linear structure. The proposed work employs a combinational logic design of S-Box implemented in Virtex II FPGA chip. The...
A low-complexity systolic-array architecture is proposed for obtaining multiple(N) broadband radio-frequency (RF) beams in smart antenna arrays. The N-beam 2D IIR digital filter is based on the concept of 2D passive ladder network resonance, leading to differential-form implementations which are highly-suitable for RF throughput levels. The proposed beamformers are converted to differential-form discrete...
Using IEEE 1588 for highly accurate clock synchronization between nodes of a distributed system has become a widely accepted approach. IEEE 802.3/Ethernet is frequently utilized as communication layer to exchange the Precision Time Protocol (PTP) messages specified in the IEEE 1588 standard. 10/100/1000 MBit Ethernet communication is commonly used by now. In contrast, fiber optics based 10 GBit Ethernet...
This paper presents a modified pipeline single-path delay feedback (SDF) fast Fourier transform (FFT) architecture. The canonic signed digit (CSD) representation is used to design the function of complex multiplier, which is the main function block in the FFT processor. The processor of a 16-bit 16-point pipeline FFT is realized on the Xilinx Virtex-4 FPGAs. The achieved maximum clock frequency is...
In this work, FPGA implementation of the compression function for four of the second round candidates of the SHA-3 competition are presented. All implementations w ere performed using the same technology and optimization techniques to present a fair comparison between the candidates. Achieved results are compared with similar implementations to provide a comprehensive comparison of candidates performance...
Previously, a two-step approach to perform the cyclic redundancy check (CRC) computation in hardware was presented. In that approach, an architecture is constructed from a suitable multiple polynomial for a fixed generator polynomial and input size. In this paper, we revisit the two-step approach and suggest a modification to its architecture. First, we propose retiming the second step to the delay...
Network security applications such as to detect malware, security breaches, and covert channels require packet inspection and processing. Performing these functions at very high network line rates and low power is critical to safe guarding enterprise networks from various cyber-security threats. Solutions based on FPGA and single or multi-core CPUs has several limitations with regards to power and...
This paper presents FPGA implementations of add/subtract algorithms for 10's complement BCD numbers. Carry-chain type circuits have been designed on 6-input LUT's Xilinx Virtex-5 FPGA technologies. Some new concepts are reviewed to compute the P and G functions for carry-chain optimization purposes. Designs are presented with the corresponding time performances and area consumption figures. Results...
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