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A compact negative bias temperature instability (NBTI) model is presented by iteratively solving the RD equations in a simple way. The new compact model can handle arbitrary stress conditions without solving time-consuming equations, and is hence, suitable for analogue/mixed-signal NBTI simulations in SPICE-like environments. The model has been implemented in Cadence ADE with Verilog-A and also takes...
In this paper, a 60 GHz CMOS on-chip dipole antenna with helium-3 ion irradiated silicon substrate is designed using knowledge of electromagnetic simulation modeling. Rectangular region with 500 um × 1000 um around the dipole is irradiated by helium-3 ion and conductivity is reduced to 0.01 S/m (1 k Ohm cm). The width of dipole section is wide for broad bandwidth and reduction of conductor loss. There...
This paper is to study the characteristics of nanowire-CMOS and effect of increasing of numbers of nanowires in transistors on the nanowire-CMOS characteristics. This study used MuGFET simulation tool to produce the characteristics of nanowire transistors and used as input to MATLAB software to produce the characteristics of nanowire-CMOS. Increasing channel nanowires in P-channel transistor tends...
We present a generic method for analyzing the effect of process variability in nanoscale circuits. The proposed framework uses kernel and a generic tail probability estimator to eliminate the need for a-priori density choice for the nature of circuit variation. This allows capturing the true nature of the circuit variation from a few random samples of its observed responses. The data-driven, non-parametric,...
This paper introduces a novel current sense amplifier (CSA) in sub-32nm fully depleted (FD) double-gate (DG) silicon-on-insulator (SOI) technology with planar independent self-aligned gates. A new architecture is proposed which takes advantage of the back gate in order to improve circuit properties. Compared to the reference circuit, the new architecture proves to be faster (21% sensing delay decrease),...
Transconductance (gm) enhancement in n-type and p-type nanowire field-effect-transistors (nwFETs) is demonstrated by introducing controlled tensile strain into channel regions by pattern dependant oxidation (PADOX). Values of gm are enhanced relative to control devices by a factor of 1.5 in p-nwFETs and 3.0 in n-nwFETs. Strain distributions calculated by a three-dimensional molecular dynamics simulation...
This paper presents an analytical modeling of ballistic and quasi-ballistic transport, implemented in Verilog-A environment and used for circuit simulation. Our model is based on the Lundstrompsilas approach and uses an expression of the backscattering coefficient given by the flux method. The model takes also into account short channel effects and tales into account the effects of different scattering...
Advances in micromachining technology can facilitate the integration of SAW (Surface Acoustic Wave) devices and CMOS circuitry on IC scale substrate for Monolithic fabrication. The optimal design and performance of these filters can be reached by using new Smart materials. The key component in the structure of the SAW device is the piezoelectric materials used which depends mainly on some important...
Simple ring-oscillator circuit has been used to estimate the degradation in circuit performance due to negative bias temperature instability (NBTI) effect but it fails to isolate the degradation from the NBTI for PMOS and the positive bias temperature instability (PBTI) for NMOS in high-K dielectric/metal gate CMOS technology. In this paper, we propose new circuit structures which monitor the NBTI...
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