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In this paper, a low complexity high quality motion estimation architecture design was proposed for MPEG-4 AVC/H.264 video coding applications. The proposed design is based on a low complexity algorithm that reduces over 90% of complexity at the cost of 0.06968dB and 0.08296dB PSNR drop as compared to JM9.3 full search with a plusmn32 search range at CIF and D1 formats, respectively. Besides, the...
A 5mW MPEG4 SP encoder is implemented on a 7.7mm2 die in 0.18mum CMOS technology. It encodes CIF 30frames/s in real-time at 9.5MHz using 5mW at 1.3V and VGA 30frames/s at 28.5MHz uses 18mW at 1.4V. This chip employs a 2D bandwidth-sharing ME design, content-aware DCT/IDCT, and clock gating techniques to minimize power consumption
This paper presents an efficient real time variable block size motion estimation (VBSME) ASIC chip, which represents a step to an H.264/AVC full encoder on chip. The proposed architecture is a SIMD architecture integrated with embedded SRAMs on one chip. The architecture has been prototyped using the TSMC 0.18 mum CMOS technology. It processes 31 CIF frames per second with 122 MHz clock frequency...
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