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A V-band sub-harmonic mixer with an integrated frequency doubler and a 180o out-of-phase splitter using standard 0.13 μm CMOS technology is reported. The sub-harmonic mixer comprises a current-reused bleeding mixer, a baseband amplifier, a 180° (Wilkinson-power-divider-based) out-of-phase splitter, and a frequency doubler. The mixer consumed 31.5 mW and achieved input return loss at RF port better...
Silicon-controlled rectifier (SCR) has been reported with the good electrostatic discharge (ESD) robustness under the lower parasitic capacitance among ESD devices in CMOS technology. To correctly predict the performances of SCR-based ESD-protected RF circuit, it is essential for RF circuit design with accurate model of SCR device. The small-signal model of SCR in RF frequency band is proposed in...
Stack-transistor structure is often used in RF applications for higher power handling capability and/or isolation. LDMOSFET may provide similar advantages with smaller device area and lower series resistance. The purpose of this work is extracting the RF parameters of a LDMOSFET and design a RF switching circuit with these parameters. The design trade-off between LDMOS and CMOS technologies was discussed...
A production released complementary-SiGe BiCMOS technology on SOI has been developed for high speed analog and RFIC applications. It features matched SiGe:C PNP and NPN transistors. The PNP shows cutting edge performance metrics with β·VA = 17,000 and near record fT·BVCEO ≥ 195GHz·V for a 5V process while demonstrating best in class linearity on a fully differential amplifier design. A modular process...
An extended true-single-phase-clock (E-TSPC) dual-modulus prescaler with a division ratio of 2 and 3 employs the forward body biasing (FBB) technique for achieving efficient on-the-fly speed and power control. The circuit is implemented in 0.25 urn CMOS. With the forward body bias voltage of 0.7 V applied to N- and P-FET's, the maximum operating frequency is improved by 80 and 87 % in the divide-by-2...
A 60-GHz receiver front-end with an integrated 180° out-of-phase Wilkinson power divider using standard 0.13 μm CMOS technology is reported. The receiver front-end comprises a wideband low-noise amplifier (LNA) with 12.4-dB gain, a current-reused bleeding mixer, a baseband amplifier, and a 180° out-of-phase Wilkinson power divider. The receiver front-end consumed 50.2 mW and achieved input return...
This paper presents the RFIC design that uses TSMC 0.18 ??m CMOS process to implement a DVB-H RF tuner. The design is based on a dual-conversion zero-IF architecture. Compared to the conventional up-down architecture, this adopted architecture has the advantages of no IF SAW filter but still can easily reject the image signal. To pass the protection-ratio specification, the most challenging one in...
A comprehensive study is presented to compare the effects between flip-chip and wire-bond packages on a front-end cascode low-noise amplifier (LNA) in a 2.4 GHz CMOS wireless local area network (WLAN) receiver. To construct the package electrical models, specific modeling dies are designed to help extract the equivalent-circuit elements from measured S-parameters for chip-package interconnects. Furthermore,...
The design and characterization of a CMOS-MEMS variable capacitor is presented. Measured results demonstrate a tuning ratio of 6.9:1, a quality factor of 28 at 3 GHz, and a self-resonant frequency of 11 GHz, with sub-50 fF parasitic capacitance. Simulations of two frequency-reconfigurable circuits, a low-noise amplifier and a power amplifier, show the importance of low parasitic capacitance for practical...
The scarcity of available frequency spectrum continues to motivate the development of new radio systems capable of adapting to local conditions. One approach to identifying available frequency spectrum is to employ an on-chip radio-frequency spectrum analyzer. In particular, the present article addresses the design of an experimental successive detection log video amplifier (SDLVA) to generate logarithmic...
As CMOS scales down and sees is cost per mm2 increasing, area-aware RF design solutions are called for. Integrated inductors with multiple taps allow for low-area multi-band RF circuit design. This work reports on the design of these inductors and provides modelling and extraction procedures demonstrated on 4-port measurements. Additionally, the application of such inductors is demonstrated on a low-area...
The effects of 63 MeV proton irradiation on 65nm Silicon-On-Insulator (SOI) CMOS technology are presented for the first time. The radiation response of the CMOS devices was investigated up to an equivalent total gamma dose of 4.1 Mrad (SiO2). We analyze the implications of proton irradiation on RF performance of these devices. The cut-off frequency is degraded due to post-irradiation degradation of...
Real-world realization of RF SoC has been hindered by the lack of high-performance, compact and tunable RF passive devices that are truly CMOS-compatible. This paper presents advances in low-temperature metal MEMS techniques developed to design and fabricate various high-performance RF passives for post-CMOS integration with RF SoC. Constructed with electroplated metal, the RF MEMS passives are suspended...
This paper presents a feasibility study on VCO using RF SiP technology, which is an RF application of stacked SiP. An off-chip inductor is implemented in a separated chip, and measured Q factor is 130. A phase noise is -119 dBc/Hz at 1 MHz offset for a 5.84-GHz carrier frequency, and frequency tuning range is 5.73 GHz-5.95 GHz. Power consumption is 1.93 mW, and 180 nm CMOS process is utilized. FOM...
Based on hardware measurement of 45nm RFCMOS and 130nm SiGe BiCMOS wafers, we present the first experimental investigation of the accuracy of various de-embedding techniques for high-frequency (up to 110GHz) on-wafer s-parameter characterization. The results clearly show that 4-port COMPLETE de-embedding offers accurate results only if the non-ideality of resistor standards is properly taken into...
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