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In this paper, a distributed amplifier (DA) with a feed forward path is presented to reduce noise effects of input matching termination at the output. The proposed active termination (AT) technique also improves the amplifier gain without increasing its power consumption. To validate the introduced method, a four-stage wideband actively terminated DA (ATDA) is designed in a 0.18μm CMOS technology...
A 0.18 μm CMOS RF receiver front-end applying in DSRC systems is presented in this paper. The proposed receiver front-end includes the current-reused LNA, the folded Giber cell mixer, and the Colpitts VCO. Also, this paper presents the design methodology and application of the transformer balun for RFIC. The measured results of the proposed receiver front-end show the input return loss of 30.5 dB,...
This paper presents the design of a 2-16 GHz ultra wide band low noise amplifier (UWB LNA). The proposed LNA has a gain of 11.5 ± 0.85 dB with NF less than 2.82 dB. Good input and output impedance matching, good isolation and linearity are achieved over the operating frequency band. The proposed UWB LNA consumes 18.14 mW of power from 1.8 V supply. This UWB LNA is designed and simulated in 0.18 μm...
In this paper, a broadband CMOS differential LNA for DC~2 GHz software defined radio is proposed. The channel thermal noise and the flicker noise of input MOSFET is canceled by exploiting a noise-canceling technique. A lower noise figure and an excellent wide-band input matching can be achieved at the same time. Moreover, the distortions introduced by input MOSFET can be partly cancelled using the...
This paper presents symmetric offset stack Marchand single and dual baluns that are designed, analyzed, and implemented in a 0.18-μm CMOS process to verify the feasibility. Both single and dual baluns achieve measured bandwidths (BWs) of over 110% and 90%, and insertion losses of less than 4.4 and 7.4 dB at 38 GHz. The amplitude imbalance and phase imbalance of single and dual baluns are less than...
In this paper, we proposed a low noise amplifier (LNA) for ultra wideband (UWB) application using TSMC 0.18μm CMOS technology. To satisfy the wide input matching, LC high-pass filter matching network is utilized in the first stage. To obtain the low power characteristic, folded-cascode with current reused technique is utilized in the second stage. The designed UWB LNA has the voltage gain of 17.6...
A fully integrated 0.18um CMOS Low Noise Amplifier (LNA) with Notch Filter for interference rejection at 5-6 GHz in UWB systems is presented. The notch filter comprises a series LC resonance circuit, which with a resistance cancelation approach yields excellent attenuating characteristics. The post layout simulation of this circuit is able to achieve more than 25 dB of attenuation at 5.6 GHz. The...
A single inductor matching network that carried low noise is designed to achieve the input wideband matching. This way has lower complexity that reduces chip area and holds the good reflection coefficient. Besides, the current reuse technique was used to achieve low power consumption. The design is simulated by Taiwan Semiconductor Manufacturing Company (TSMC) 0.18μm RF CMOS process. Through a 1V/5...
This paper presents a 2 - 13GHz low-voltage broadband down-conversion mixer with an active balun for UWB radio. The mixer with an active balun is fabricated in the 0.18 μm 1P6M standard CMOS process. The mixer with active balun consumes 15.2 mW from a 1.2 V supply. This mixer was achieved by using a folded-mixer and a peaking inductor technique. This technique can double the 3 dB bandwidth...
In this paper, the amplifier path consisting of the low-noise amplifier (LNA) and programmable-gain amplifier (PGA) is designed. For lower input-referred noise power, the active input impedance termination should be indispensable. The novel circuit is proposed for high-performance LNA. The PGA is designed to cover the operating range of 48dB. The analog front-end is designed and verified in a 0.18-μm...
Design, development and simulation results of an interdigitated metal-fingers capacitors in 0.18μm RF-CMOS technology that are exploiting both lateral and vertical metal-metal capacitances are presented. Two RF-CMOS capacitors are designed specifically for applications in a 2.45GHz power splitter circuit. Five metal RF-CMOS layers are used to design two capacitors of 1.39pF and 2.2pF, consisting of...
In this paper, a fully integrated CMOS receiver front-end for 2.4-GHz Band IEEE 802.15.4 standard in a 0.18-μm CMOS technology is presented. It is comprised of a low-power CMOS LNA including a common-gate stage with modified input matching and active balanced down-conversion mixer which uses the current bleeding technique and an extra LC filter to improve the noise figure (NF) and conversion gain...
In this paper a new low voltage low power class AB CMOS second generation current conveyor (CCII) based on Rail-to-Rail folded cascode Op-Amp is presented, with a great performance. The proposed CCII provides very low input impedance at X-port, very high input impedance at Y-port, accurate voltage and current tracking with low offset, and wide bandwidth. As an application, a four quadrant analog multiplier...
A 2.4 GHz reconfigurable CMOS power amplifier to minimize antenna mismatch effects is presented. The PA is implemented by using a 0.18-μm RF CMOS process, and the supply voltage is 3.3 V. The proposed PA is compared to a conventional PA with a fixed matching network. By utilizing the proposed reconfigurable matching network, both the efficiency and the output power are improved under an...
This paper presents a dual-path noise-cancelling (DPNC) LNA, which is designed for low power wireless sensor network (WSN) applications and operates at 2.4GHz band. The proposed DPNC LNA can effectively cancel internal circuit noise while consuming less power by gm-boosted technique. The measured voltage gain and NF are 22dB and 3.7dB, respectively. IIP3 is +8dBm and consumes 1.2mW with a 1.0V single...
One band switchable low noise amplifier (LNA) is designed for wideband applications. The proposed band switchable LNA has two switchable bands. The design consists of a input matching circuit, two cascode common-source amplifiers and an output buffer for measurement. The proposed LNA is designed with two switching capacitors as loading that use NMOS to make high quality factor. The proposed LNA gives...
A 3-5GHz CMOS low noise amplifier (LNA) for ultra wide band (UWB) receiver based on CMOS 0.18μm process is presented in this paper. To achieve low-power consumption and low noise, the proposed LNA employs current-reused technique via a PMOS cascade stage. The LNA provides a maximum forward gain (S21) of 11dB while drawing 6mW from 1.2-V supply voltage. The LNA achieves 2.6-3.9dB noise figure (NF)...
A low noise amplifier (LNA) is proposed for a 35GHz ultra-wideband (UWB) system. The combination of a common-gate (CG) input stage and a common-source (CS) input cascode stage is exploited with a modified form of noise cancellation. The proposed LNA is implemented in a 0.18μm CMOS technology and achieves a power gain of 18dB, an average noise figure of 3.3dB, and better than -11dB of input/output...
This paper presents a 0.9GHz-10GHz Ultra Wideband Low Noise Amplifier (LNA) designed for software-defined-radios (SDR). Capacitive cross coupling (CCC) is used at both input stage and cascade stage for wideband input impedance matching and small noise figure (NF). A combination of inductor peaking load and series inductor between the cascade stages of LNA is employed for a flat gain and enhanced input...
This paper describes a high efficiency rectifier circuit for passive UHF radio frequency identification (RFID) applications. The simulation and measurement show efficiency of 30.7% and 15% at low input power level respectively. The rectifier was fabricated in a standard 0.18um CMOS process and its core circuit occupied 0.169×0.137 mm2 silicon area.
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