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Single-ended and differential low-noise amplifiers (LNAs), designed in 0.18 μm CMOS for operation at 24 GHz, are introduced in this paper. Novel, high-Q series-stub transmission lines (SSTLs) are used in the matching networks of both LNAs. This SSTL structure shows a notable Q factor improvement over the commonly used spiral inductor, which helps to minimize the losses and noise produced in the LNA...
This paper examines the design of a 10 Gbps transimpedance amplifier (TIA) in 0.18 mum CMOS technology. In order to compensate for the high parasitic capacitances in the CMOS process, this design uses a shunt and series inductive peaking technique to achieve the required transimpedance bandwidth. A noise analysis on the input stage of the TIA is shown. This noise model is used to determine the optimum...
Low power CMOS RF digitally programmable gain amplifiers for dual-band (Band-III and L-Band) DAB/T-DMB receiver IC are implemented using 0.18 mum CMOS process. For a stable operation among large interference situation, it is required to have wide gain range and fine resolution in RF domain. In order to meet such requirements, various programmable gain amplifier architectures are proposed. Also employing...
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