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Analog and digital feedforward swing-reduction techniques optimize the power consumption of this 2nd-order DeltaSigma modulator. The 0.18um CMOS prototype uses 2 telescopic OTAs and 2 ADCs requiring 10 comparators. The technique makes the modulator equivalent to a 4b architecture. The OSR is 33 and the clock frequency is 144MHz
A 2nd-order DeltaSigma modulator that obtains low power consumption by 2-channel time-interleaving is described. The main channel requires 2 opamps whereas the second channel does not use any active elements. This structure is robust to channel mismatches and uses a simple clocking scheme. The circuit is integrated in a 0.18mum CMOS process and occupies an active area of 1.1mm2
A 0.5V 3rd-order 1b fully differential CT DeltaSigma modulator in a 0.18mum CMOS process is presented. A special return-to-open DAC, a body-input gate-clocked comparator, and body-input OTAs for the active-RC loop filter enable the ultra-low voltage operation. The 0.6mm 2 chip consumes 370muW and achieves a peak SNDR of 74dB in a 25kHz BW
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