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Research and development activities are ongoing to design the front-end chip for the hybrid pixel sensors that will equip the Micro-Vertex Detector of the PANDA experiment at GSI. In its final implementation the ASIC will incorporate more than lOfe channels. The analog and digital electronics necessary to amplify the detector signal and to digitize the charge information with low power consumption...
The last member of the IDeF-X ASIC family is presented: IDeF-X SX0 a 32-channel front end ASIC designed for the readout of Cadmium Telluride (CdTe) and Cadmium Zinc Telluride (CdZnTe) Detectors. It has been designed in the standard AMS CMOS 0.35 ??m process technology. The ASIC has been optimized to reduce the power consumption which is now 600 ??W per channel; it is five times lower than the power...
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