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An AES is the most popular security algorithm and it is required to improve the performance of AES with increasing the demand of internet security. AES is a symmetric key algorithm in which only one key is requires for encryption and decryption process, key must be same. The AES implementation is possible for software and hardware but hardware implementation has better speed in comparison to software...
Algorithms for data encryption are one of the most important parts of modern communication systems. In this paper the results of hardware implementation of AES256 and TDES algorithms are presented. AES256 and TDES are implemented as an IP core with AXI interface because of constant growth of data transfer requirements in modern embedded systems, in order to improve their capability. Beside details...
One of the major problems in communication is the secure transportation of data over communication protocols. This paper presents a feasible resolution for Rijindael's encryption and decryption using VHDL for FPGA (cyclone III) & ‘C’ running over Nios II processor. The Nios II is a versatile embedded processor which is high performance, of lower cost and power consumption, has low complexity combining...
One of the major problems in communication is the secure transportation of data over communication protocols. This paper presents a feasible resolution for Rijindael's encryption and decryption using VHDL for FPGA (cyclone III) & ‘C’ running over Nios II processor. The Nios II is a versatile embedded processor which is high performance, of lower cost and power consumption, has low complexity combining...
Information Security is a major issue worldwide. Various steps are being taken to improve and upgrade security measures. Border crossings across countries have become one of them. Therefore the use of traditional passports has lead to an improvement in the name of E-passports. E-passports are a more secured and are denoted by a symbol. E-passports contain a small chip which stores the data of passport...
In this project, a hardware implementation of the AES-256 encryption and decryption algorithm is proposed. The AES cryptography algorithm can be used to encryption and decryption blocks of 128 bits and is capable of using cipher keys of 256 bits. Feature of the proposed pipeline design is depending on the round keys, which are consumed different round of encryption, are generated in parallel way with...
AES represents the algorithm for advanced encryption standard consistof different operations required in the steps of encryption and decryption. The proposed architecture is based on optimizing area in terms of reducing no of slices required for design of AES algorithm in VHDL. This paper presents AES-128 bit algorithm design consist of 128 bit symmetric key. The AES implementation, merging technique...
With worldwide communication of the private and confidential data over the computing networks or internet, there is always a chance of threat of data confidentality, data integrity and also of data availability. Information has become one of the most important assests in growing demand of need to store every single importance of events in everyday of our life. Encipherment is one of the important...
For secure data transmission cryptographic algorithms are used for many applications. This paper introduces optimized hardware implementation of area and speed improvement for the block cipher Advanced Encryption Standard (AES-128) using Field Programmable Graphic Array (FPGA). As AES has four transformations among them sub-byte and mix-column transformation are key challenges to implement in terms...
This paper presents a hardware implementation of the PRINCE block cipher in Field Programmable Gate Array (FPGA). In many security applications, the software implementations of cryptographic algorithms are slow and inefficient. In order to solve the problems, a new FPGA architecture was proposed to speed up the performance and flexibility of PRINCE algorithm. The concurrent computing design allows...
DVB-CSA (Digital Video Broadcast - Common Scrambling Algorithm) is encryption method commonly used to protect the paid channels of digital television. The paper presents a study of its implementation in specialized digital hardware. The algorithm was successfully converted to logic architecture, coded in hardware description language (VHDL), verified and synthesized for programmable logic device (FPGA)...
DVB-CSA (Digital Video Broadcast - Common Scrambling Algorithm) is encryption method commonly used to protect the paid channels of digital television. The paper presents a study of its implementation in specialized digital hardware. The algorithm was successfully converted to logic architecture, coded in hardware description language (VHDL), verified and synthesized for programmable logic device (FPGA).
Cryptography is one of the fundamental components for secure communication of data and authentication. However, cryptographic algorithms impose tremendous processing power demands that can be a bottleneck in high-speed networks. The implementation of a cryptographic algorithm must achieve high processing rate to fully utilize the available network bandwidth. To follow the variety and the rapid changes...
Advanced Encryption Standard, a federal information processing standard is an approved cryptographic algorithm that can be used to protect electronic data. The AES can be programmed in software or built with pure hardware. However field programmable gate array offers a quicker and more customizable solution. This paper presents the AES algorithm with regard to FPGA and the very high speed integrated...
This paper presents detailed methodology for performing simulated Power Analysis Attacks (PAAs) on gate level models of cryptographic components with Synopsys design tools. First the Advanced Encryption Standard (AES) hardware model is developed for the experiment using VHDL. The model is then synthesized with Synopsys DesignCompiler and the 130-nm CMOS standard cell library. Simulated instantaneous...
This paper describes the field programmable gate array (FPGA) implementation of Rijndael algorithm based on a novel design of S-box built using reduced residue of prime numbers. The objective is to present an efficient hardware implementation of Rijndael using very high speed integrated circuit hardware description language (VHDL). The novel S-box look up table (LUT) entries forms a set of reduced...
Advanced Encryption Standard (AES), a Federal Information Processing Standard (FIPS), is an approved cryptographic algorithm that can be used to protect electronic data. The AES can be programmed in software or built with pure hardware. However Field Programmable Gate Arrays (FPGAs) offer a quicker and more customizable solution. This paper presents the AES algorithm with regard to FPGA and the Very...
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