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Open defects are responsible for a significant number of failures affecting present CMOS technologies. Furthermore, they are becoming more common as technologies are scaled down due to changes in materials and fabrication steps of ICs manufacturing processes. In this chapter, open defects are classified according to their location and resistive nature. The behavior of such defects affecting interconnect...
Bridging defects are responsible for a large percentage of failures in CMOS technologies and their impact in nanometer technologies with highly dense interconnect structures is expected to increase. In this chapter, a survey of the key developments in modeling bridging defects and their implications in test and diagnosis are presented. An overview of the historical developments of these models from...
In this chapter fault models used to model the effects of defects causing excessive circuit delays are discussed. Methods to generate tests to detect modeled faults and design for test methods to improve fault coverage are reviewed. Current work in detecting what are called small delay defects is discussed.
Fault simulation and ATPG are core algorithms in the context of digital hardware test. Their deployment for resistive fault models is challenging as the behavior of the defective circuit depends on the defect resistance and the number of possible resistances is infinite. In this chapter, we show that efficient fault simulation and ATPG algorithms are feasible for resistive bridging faults. Application...
To cope with the numerous defect mechanisms in nanoelectronic technology, more and more complex fault models have been introduced. Each model comes with its own properties and algorithms for test generation and logic diagnosis. In diagnosis, however, the defect mechanisms of a failing device are not known in advance, and algorithms that assume a specific fault model may fail. Therefore, diagnosis...
Semiconductor memories have been always used to push silicon technology at its limit. This makes these devices extremely sensible to physical defects and environmental influences that may severely compromise their correct behavior. Efficient and detailed testing procedures for memory devices are therefore mandatory. As physical examination of memory designs is too complex, working with models capable...
Power consumption of circuits and systems receives more and more attention. In test mode, power consumption is even more critical than in system model and has severe impact on reliability, yield and test costs. This chapter describes the different types and sources of test power. Power-aware techniques for test pattern generation, design for test and test data compression are presented which allow...
Dependable systems are obtained by means of extensive testing procedures and the incorporation of fault tolerance mechanisms encompassing error detection (on-line testing) and system recovery. In that context, the characterization of fault models that are both tractable and representative of actual faults constitute an essential basis upon which one can efficiently verify, design or assess dependable...
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