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Field-programmable gate arrays (FPGAs) are now a standard medium for implementing digital circuits in a wide variety of markets including telecommunications, automotive systems, high-performance computers and consumer electronics. They offer lower non-recurring engineering (NRE) costs and faster time to market than more customized approaches such as full-custom VLSI or application-specific integrated...
One goal of this book is to measure and understand the FPGA to ASIC gap. The gap is affected by many aspects of FPGA design including the FPGA’s architecture, the circuit structures used to implement the architectural features, and the sizing of the transistors within those circuits. In this chapter, the terminology and the conventional design approaches for these three areas are summarized. As well,...
The goal of this research is to explore the area, performance and power consumption gap between FPGAs and standard cell ASICs. The first step in this process is measuring the FPGA to ASIC gap. In the previous chapter, we described how all prior published attempts to make this comparison were superficial since none of those works focused exclusively on measuring this gap. In this chapter, we present...
The large area, performance and power gap between FPGAs and ASICs reported in the previous chapter clearly demonstrates the need for continued research aimed at narrowing this gap. While narrowing the gap will certainly require innovative improvements to FPGA architectures, it is also instructive to gain a more thorough understanding of the existing gap and the trade-offs that can be made with current...
The measurement and analysis of the FPGA to ASIC gap in Chapter 3 found that there is significant room for improvement in the area, performance and power consumption of FPGAs. Whether it is possible to close the gap between FPGAs and ASICs is an important open question. Our analysis in Chapter 3 (by necessity) focused on a single FPGA design but there are in fact a multitude of different FPGA designs...
This chapter continues the exploration of area and delay trade-offs started in the previous chapter. That chapter focused on architectural and process technology selection as those choices have been the conventional approach for enabling area and delay trade-offs. In each of the FPGA designs considered in that exploration, all the transistor sizes in the design were optimized using the tool described...
The focus of this book was on gaining a better understanding of the area, performance and power consumption gap between FPGAs and ASICs. The first step in doing this was to measure the gap. While we found that heterogeneous hard blocks can be useful tools in narrowing the area gap, it is still true that the area, performance and power gap for soft logic remains large. To address this large gap, the...
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