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The OCAPI-XL based approach was applied in the MPEG-4 video decoder design case with aim to validate the system level reconfigurability extensions on a typical multimedia application. The MPEG-4 case represents a scenario where tasks are relocated between software and reconfigurable hardware depending on the level of quality of service requested by the user. The MPEG-4 video decoder has been implemented...
In this chapter the prototyping of a reconfigurable System-on-Chip realizing the HIPERLAN/2 WLAN system is discussed. In this case reconfigurable hardware will be exploited to introduce post-fabrication functional upgrades. For the prototyping a commercial platform using components-off-the-shelf has been used. The design flow and system level design methods described in the previous chapters were...
The SystemC based approach and extensions are applied in the WCDMA design case in order to validate it at the system level, and to get experiences on the detailed and implementation design of reconfigurability on the selected Virtex II Pro demonstrator platform. The WCDMA detector case represents a reconfiguration scenario of applying partial dynamic reconfiguration in a mobile terminal.
This chapter introduces the reader to main concepts of reconfigurable computing and reconfigurable hardware. Different types of reconfiguration are discussed. A detailed classification of reconfigurable architectures with respect to the granularity of their building blocks, the reconfiguration scheme and the system level coupling is also presented.
This chapter presents cases where reconfigurable hardware can be exploited for the efficient realization of wireless multimedia communication systems. The various scenarios described are referring to (a) the DLC/MAC layer and the baseband part of the physical layer of HIPERLAN/2 and IEEE 802.11a WLAN protocols, and (b) the application layer of a sophisticated personal device. The goal of this chapter...
A large number of reconfigurable hardware technologies have been proposed both in academia and commercially (some of them in their first market steps). They can be roughly classified in three major categories: a) Field Programmable Gate Arrays (FPGAs), b) integrated circuit devices with embedded reconfigurable resources and c) embedded reconfigurable cores for Systems-on-Chip (SoCs). In this chapter...
A top down design flow for heterogeneous reconfigurable Systems-on-Chip is presented in this chapter. The design flow covers issues related to system level design down to back end technology dependent design stages. Emphasis is given on issues related to reconfiguration, especially in system level where existing flows do not cover such aspects.
This chapter describes the SystemC based modelling techniques and tools that support the design of reconfigurable systems-on-chip (SoC). For designing of reconfigurable parts at system level, we developed: 1) an estimation method and tool for estimating the execution time and the resource consumption of function blocks on dynamically reconfigurable logic to support system partitioning, 2) a SystemC...
This chapter describes the OCAPI-XL based modelling techniques and tools that support the design of reconfigurable systems-on-chip (SoC). To allow modeling of reconfigurability features at system level, we developed: 1) new software process type in OCAPI-XL, 2) coupling of OCAPI-XL to SystemC for co-simulation, and 3) context switching from one resource towards another (software, reconfigurable hardware).
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