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A new architecture of monolithic THz imager adopting a VCO-based signal processing is proposed, and the enhancement of signal-to-noise ratio is analyzed. The 0.5/1.5 THz imagers, implemented in a 65 nm CMOS, show the lower noise equivalent power (NEP) than that of the detector itself, presenting the best NEP among the state-of-the-art imagers. The fully integrated THz imagers do not require external...
This paper presents a dual-loop 2-step ZQ calibration scheme with 20nm DRAM process to support dedicated supply voltage (VDD, VDDQ). The proposed calibration scheme maintains a target value of on-die termination (ODT) in DQ/CA regardless of the supply-voltage variations which are caused by dynamic voltage frequency switching (DVFS) and alleviates the calibration time which is increased by insertion...
Asymmetric Error Reduction Huffman Coding (AERH) is proposed for MLC/3LC NAND flash memory used as SSD cache in the tiered hierarchical storage. AERH compresses data, reduces asymmetric memory cell errors by modulating Vth distribution and thus enhances reliability and endurance of memory cells. AERH decreases data-retention errors by 72.6% and 82.6% of MLC and 3LC NAND flash, respectively. In addition,...
Word-line Batch Vth Modulation (WBVM) is proposed as a comprehensive solution for both write-hot and cold data to improve the reliability of Triple Level Cell (TLC) NAND Flash memories. For write-hot data, WBVM Vth score modulation decreases the program-disturb errors by 49% and enhances the endurance by 1.8-times of 2D-TLC NAND Flash. On the other hand, for write-cold data, WBVM BER score modulation...
We propose a column-based split cell-VSS (CS-CVSS) data-aware write-assisted (DAW A) 9T ultra-low voltage SRAM with enhanced read sensing margin in 28nm FDSOI technology. The proposed write-assist technique (CS-CVSS and DAWA) improve both half-select SNM and write margin. The proposed 3T low leakage read port enhances read sensing margin by minimizing bitline leakage through negative gate to source...
This paper presents an energy-efficient symmetric block-wise concatenated-BCH (SBC-BCH) decoder architecture for energy-starving mobile storages. The proposed 4KB SBC-BCH code remarkably enhances the hard-decision-based error-correcting performance to defer the energy-consuming memorysensing operations for generating the soft-decision values, which are necessary to prolong the lifetime of flash memories...
This paper designed a 1-Mb HfOx-based embedded Resistive Random Access Memory (RRAM) device with a one-transistor-one-resistor (1T1R) structure, and systematically investigated its working temperature range. It noted that this embedded RRAM macro has a 1.6X working temperature range than previous design for some extreme environment. Using the peripheral-assisted technique, it can enable the error...
This paper describes a WiFi/BT combo SoC with integrated dual-band PAs, LNAs and T/R switches, supporting concurrent receiving for improved throughput by 30% in dense networking environment of 2.4GHz ISM band and wide-range transmitting capability (>20dB) while keeping good output power accuracy and PA power efficiency. The measured 2.4GHz/5GHz WiFi 54Mbps RX sensitivity is −78.2/−78.1dBm and Pout...
This paper describes a digital-mapping DDFS with a frequency tuning and amplitude resolutions of 24-bits and 10-bits respectively. This Si-CMOS-MMIC is the first solution supporting a sampling rate of 7GS/s and frequency, phase and amplitude modulations in the digital domain. It includes a 14-bits pipelined ripple-carry adder and a 10-bits high-speed multiplier for phase and amplitude modulations...
A narrowband low-power low-sensitivity, IoT TxRx compliant to ARIB STD-T-67 & T-30, is presented. It employs (1) an injection locked IQ-divider without power-hungry high speed logic gates and flip flops to generate 25% duty cycle LO that drives the mixer following a simultaneously noise and impedance matched gm-boosted LNA, and (2) A dedicated pilot-less direct automatic frequency correction of...
This paper reports a 3.0 THz detector which can detect the terahertz wave radiated by a quantum cascade laser (QCL) working at pulse mode. The detector was implemented in a 65 nm silicon CMOS process. The chip size is 1.5×l.5 mm2 including bonding pads. THz detector using FET is based on plasma wave theory proposed by Dyakonov and Shur which allows detection of THz radiations far beyond the FET devices...
A 0.6-V, 200-kbps, 429-MHz ultra-low-power FSK transceiver (TRX) is presented. The receiver (RX) adopts a frequency-to-time based demodulator, which detects high or low frequency to determine data output level. The proposed RX achieves −85-dBm sensitivity at 0.1% BER and draws 0.146 mW. A 38.7% global efficiency, 429-MHz FSK transmitter (TX) is also reported in this paper. To remove the power-hungry...
In this paper, we propose a novel 24-transistor change-sensing flip-flop (CSFF) for ultra-low power applications. With the aid of an internal change-sensing unit, the proposed CSFF eliminates redundant transitions of internal clocked nodes when there is no change in the flip-flop content. No additional transistors are required compared to the conventional transmission-gate flip-flop (TGFF). Measurement...
We propose an on-chip bias temperature instabilities (BTI) monitor by using standard cell based unbalanced ring-oscillator (RO). The monitor consists of NAND and NOR with extremely large difference in drive strength, which enables 4.2x sensitivity to BTI compared with normal INV based RO. This originates not only from accentuation of the degraded stage with small drive strength by the dominant delay...
To reduce conservative timing margin, many timing-error detection techniques by monitoring selected critical paths had been proposed. However, traditional adaptive methods incur significant area overheads and cannot prevent the error that is forming in the current clock cycle. In this paper, a low-overhead Transition-Detector (TD) with a 9-transistor current sensing circuit is proposed. TDs are inserted...
To eliminate the worst-case timing margins, a 13-transistor holosymmetrical transition detector (HTD) is proposed for use in timing variation resilient systems. The HTD achieves low overhead and wide-voltage-range operation via monitoring the discharge at the floating node of two-stage CMOS inverters. Using local detection and global clock stalling, the system is stalled immediately for one cycle...
This paper presents a low voltage and power efficient 12-bit successive-approximation register (SAR) analog-to-digital converter (ADC). The proposed adaptive time-domain (ATD) comparator automatically adjusts its input-referred noise performance according to the intermediate residual input level (ΔVin) during conversion. Considering the noise requirement of 12-bit SAR ADC, the proposed implementation...
A Range Pre-selection Sampling (RPS) technique is introduced to reduce the input drive energy for SAR ADCs and is applied to a 10-bit 2MS/s SAR ADC in 65nm CMOS in this paper. Using the proposed RPS technique, the peak input sampling current and hence the input drive power requirement is reduced by a factor 2.4 as compared to conventional sampling (CS). Considering an ideal Class A operation for the...
This paper presents a 5-bit 2GS/s binary-search ADC. The proposed architecture prevents the use of a decoder to avoid the path delay racing between control signals and clock phases; thence the bit latency reduces to 1 single comparator delay only. We also propose a dynamic charge-steering comparator to quantize each bit quickly. Besides, we present well-balanced 1-of-N-to-Binary encoders to transform...
A 13-bit 160MS/s hybrid ADC in 65 nm CMOS is presented in this paper. By combining the pipelined, flash and SAR architectures, a hybrid ADC architecture is proposed to improve the power efficiency. An input offset storage technique of dynamic comparator is proposed to increase the conversion linearity. A reference voltage buffer with the charge compensation is proposed to save power and reduce the...
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