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A super-pixel based on-chip compression is proposed in this paper. The compression is achieved by reading only one sample for each super-pixel. The proposed technique and the corresponding circuit are simulated in MATLAB and UMC 180 nm CMOS technology, respectively. Higher values of PSNR are observed as compared to the state-of-the-art on-chip compression techniques. For the compression factor of...
We present a TCAD process and analytical model based simulation analysis to investigate the effect of different stressors on nanowire FETs. We have utilized stress profiles extracted from TCAD process simulations and calculated mobility enhancement using the second-order piezoresistive model. Our analysis includes strained CESL and strained gate fill material for a gate-last process. Our process simulations...
This work presents a self-adaptation algorithm to automatically adjust the peaking settings of a continuous-time linear equalizer (CTLE) in a high-speed PAM4 receiver. A statistical approach is adopted to improve the robustness and flexibility of the adaptation algorithm. The PAM4 top level distribution around the peak value of several consecutive top levels guides the CTLE to attain the optimal digital...
In this paper, low cost 1200V UHV LDMOS device has been proposed. As BVD and Ron are contradictory, so to make low Ron, high breakdown voltage is the challenge of this paper. The key feature of this device is the linear P-top which is used to obtain best charge balance, and increase the diffusion current to move faster in the drift region which reduces the electric field and substantially helps to...
This paper mainly presents a design of optimized (15, 4) parallel counter. When testing the design with 15 rows of inputs, synthesis report of our design performs better in respect of delay, area and power consumption than other two existing design. This result shows that processes such as partial product reduction in a multiplier or column-addition in a matrix could be more efficient, especially...
For the first time, this paper reveals and explains the detailed contribution of the main-junction lateral resistive zone to the ruggedness of high-voltage fast recovery diodes during a harsh reverse recovery. And its optimized width is discussed.
We present an energy efficient QRS detector for real-time ECG signal processing implemented in ASIC. An adaptive thresholding scheme based on forward search interval (FSI) algorithm together with simple preprocessing is proposed to accurately detect QRS peaks. The Verilog HDL codes with improved hardware utilization efficiency are validated using FPGA, achieving 99.59% sensitivity (Se) and 99.63%...
This paper presents a 77GHz, 16dBm, 13% PAE power amplifier. It is simulated in a 0.13um silicon-germanium technology with fT of 200GHz. The design technique is not the same as those which are used in traditional power amplifiers. All the matching structures are composed of short or open stubs and MIM capacitors. To get a higher output saturation power, breakdown voltage is also considered in bias...
When encrypting a single file in the CBC mode of 3DES, there is a feedback path which brings data dependency. Even much more resources are given, it does not help matters to increase the throughput of 3DES. In this paper, we propose a logic simplifying method to accelerate the throughput in the CBC mode. In the datapath, 15 levels of XORs from the critical path can be moved to the non-critical path...
In this work, we demonstrate a way to modulate threshold voltage of InGaAs Fin-structured High-electron-mobility transistors (Fin-HEMTs) by narrowing fin width of the devices. Normally-off InGaAs FinHEMT has been successfully achieved when fin width of devices is smaller than around 180 nm. Also, we introduce a theory to explain side wall gates control of FinHEMTs to modulate threshold voltage.
Correlated double sampling(CDS) operation is generally used in CMOS imaging systems, implemented by switched capacitor(SC) circuits, to get rid of reset noise and decrease flicker noise. This paper presents an optimization method for the noise performance of a CDS circuit, the advantage of which is its ability of canceling the offset of the OP involved. The structure of the CDS circuit is analyzed...
This paper presents a in situ on-chip micro tensile fracture strength tester, which is based on a thermal actuated test platform. In this test platform, tensile fracture strength could be extracted and process could be evaluated, there are two samples with same layout but fabricated under different process conditions were evaluated through this test platform and the results showed that this test platform...
A simple analytical model is proposed to estimate the optimum length of the pinned photo diode. This optimum length is defined as the length at which the optimum full well capacity and the charge transfer time are achieved simultaneously. The simulation results show good agreement with the model proposed. The conventional approach of repeated simulations is avoided using the proposed model.
A low-power high feedback factor common mode feedback technique using subthreshold MOSFETs is presented in this paper. The proposed approach is an improved version of the conventional resistive degeneration of current mirrors. The proposed technique is implemented in preamplifier which is designed in UMC 180 nm technology with 1.8V power supply and 225nA bias current. The SPICE simulations show that...
Side reservoir can improve electromigration (EM) lifetime of copper interconnects. In this work, finite element method (FEM) simulations for interconnect structures with cathode end-of-line reservoir and side reservoir respectively have been conducted to study the side reservoir effects on EM lifetime. It is demonstrated that side location is most likely to have void failure and side reservoir can...
For many years now, SOI devices have been used as microelectronic devices operating in space environment as they have limited silicon volume for charge collection. In this work, the impact of irradiation by alpha-particles with energy in the range of 0.1MeV-1MeV has been analyzed for bulk as well as SOI devices with varying SOI thickness. This work is done using 2-D TCAD with radiation parameters...
A novel positive to negative voltage converter and a novel LDO regulator are proposed in this paper. Compared with the conventional voltage converter, the proposed one has a higher efficiency for a certain process. The novel negative voltage LDO circuit has a good temperature characteristic with a simple and chip-saving control circuit. The proposed whole circuit is verified with simulation in CSMC...
This paper presents an innovative 500V LDMOS device is constructed by SCR structure, a thin oxide and poly resistor. This structure can improve the self-protection capability of LDMOS for Electrostatic Discharge (ESD), because this structure can distribute current from the drain to the poly resistor, so the transistor effect occurs earlier. After sequential ESD zapping applied on this device, lattice...
RF CMOS technology provides a platform for the production of analog, digital and RF circuits on a single chip for futuristic high-level integration. This facilitates the need for a robust compact model for RF FinFETs to study the circuits in a precise and convenient way. In this paper, we have characterized 14-nm N-channel bulk FinFETs by performing two-port S-parameter measurements. Further, BSIM-CMG...
This paper presents a wide range high efficiency fully integrated switched-capacitor DC-DC converter with fixed output spectrum targeting for noise-sensitive Internet-of-Things (IoT) applications. In order to alleviate the unpredictable output spectrum and the reduced energy efficiency of the conventional pulse-frequency modulation (PFM) and pulse-width modulation (PWM) schemes, fixed output spectrum...
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