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In this paper, we study the source drain Gaussian doping profile of strained In0.53Ga0.47AS based high electron mobility FinFET transistor (HEMT). The Gaussian doping profile is created using Pearson distribution model by setting the values of the gamma and beta parameters (the function characterizing the amorphous part of the profile). The ON current increases exponentially and the step doping also...
The paper proposes a low area 10-bit DAC for AMOLED source driver ICs. The proposed driver consists of a 7-bit gamma correction resistor-string DAC and a 3-bit sub-DAC based on programmable current cell (PCC) within the output buffer. The output buffer with 3-bit sub-DAC could implement voltage interpolation with only two differential pairs and three CMOS switches. This leads to a compact die size...
The inductively coupled coil in wireless power transfer (WPT) system is the key to optimizing the power transfer efficiency. Based on an iterative printed spiral coil (PSC) design procedure, this paper proposes a load-based design method to improve the efficiency stability for a load-variable system. The efficiency stability coefficient is defined to choose the optimal PSCs. Several pairs of PSCs...
FinFET variability, which is a small amplitude deviation caused by process, cannot be ignored with the scaling of CMOS. This work utilizes the variability as the random source of SRAM Physical Unclonable function (PUF). The impact of the variation has been simulated from device-level to circuit-level. Further research has been done with its influence on SRAM static noise margin (SNM) and SRAM PUF...
Based on the parabolic potential approach (PPA) and equivalent number of gates (ENG), a new quasi-3-D subthreshold current/swing model for the fully depleted quadruple-Gate (FDQG) MOSFET is developed. The model explicitly shows how the channel length, gate oxide thickness, and silicon film thickness affect the subthreshold current/swing behavior. The model is verified by its calculated results matching...
In this study, the threshold voltage and breakdown voltage of a double-channel AlGaN/GaN HEMT is improved. Firstly, depletion mode (D-mode) is changed to enhancement mode (E-mode) by optimizing the depth of the recessed gate, the Al ratio in the AlGaN layer, and the doping concentration of the p-doped region. Secondly, the E-mode device with highest breakdown voltage is selected, and then implemented...
Modular multiplier is the key to implement RSA algorithm. This paper proposes the design of an 8192-bit residue number system (RNS) Montgomery multiplier based on Cox-Rower architecture. To accelerate the reduction unit, we select modulo with a small Hamming weigh, and modulo are grouped by the number of Rowers. Each Rower unit only needs to support the reduction processes of one group of modulo instead...
The rise/fall time mismatch in a differential signal is responsible for a serious common-mode (CM) issue in high-speed CMOS serializer/deserializer (SERDES) transmitters (Txs). The non-linear parasitic impedance variations of the switching devices and differences in parasitic impedances in the charging and discharging loop produce deterministic spurs on the CM voltage that generate certain spectral...
An 80 Gb/s 4-level pulse amplitude modulation (PAM4) wireline receiver is presented in this paper. This receiver adopts quarter rate architecture to improve data rate and reduce power consumption. In order to reduce the complexity of the clock and data recovery (CDR) design, a voltage control oscillator (VCO) based CDR without reference clock is used. Furthermore, four BBPDs are used to sample the...
This paper presents a multi-PLL clock architecture used in a 4-lane multi-protocol serial link applications. The clock architecture consists of one public LC PLL and four standalone ring PLLs placed within each lane. A swtich capacitor array based LC VCO is used in the LC PLL to enlarge the frequency tuning range and decrease the VCO gain. A two stage pseudodifferential inverter based ring VCO with...
This paper presents a lossless compression method dealing with the data in real time kinematic (RTK) system, which is an aggregation of frame difference and dictionary compression (AFD). AFD can exert advantage of pipeline hardware; reduce the amount of data transmission as to save energy. Experiment results showed that the compression time of typical RTK data was only 0.2 milliseconds, and the average...
A fully integrated THz phase-locked loop (PLL) is proposed. It is consists of a fundamental PLL and a frequency doubler. In order to improve the oscillation frequency and reduced the phase noise, a feedback network composed of buffer amplifiers and capacitors is introduced to the voltage-controlled oscillator (VCO). The wide locking-range divider chain of PLL consists of an injection-locked frequency...
A three-dimensional MnCo2S4@NiCo(OH)2 (MCS@NCOH) core-shell nanostructure is grown on nickel foam by a simple and facile method which includes a hydrothermal treatment and an electrochemical deposition. The MnCo2S4 (MCS) nanorod arrays not only show excellent electrochemical performance by themselves, but also use as effective scaffolds to load additional active materials for enhancing the capacitance...
In this work, we investigated the photocapacitive effect of the metal-ferroelectric-insulator-semiconductor capacitors under illumination. The photocapacitive effect is mainly caused by light photon excitation, contributed from the variation of depletion charge. We suggested that the ferroelectric domains are affected by defect dipole charges formed by the interface trapped charges to lead to the...
In this paper, we introduce a real-time pressure measurement system. A soft material with gauge points is placed ahead of a micro camera, and the material's deformation reflects the pressure applied on it. The image processing circuit mainly consists of an image pre-processing module, a connected area labeled module and a centroid coordinate calculation module. Experiments are implemented to demonstrate...
This paper describes the design of a serial-link transceiver that supports various communication standards from 1.25 to 12.5Gb/s, implemented in 40nm CMOS technology. Both DC and AC coupling mode can be provided by the receiver, in which a wide range PI-based CDR is also proposed. The transceiver utilizes a 3-tap FFE, a 2-stage CTLE and an adaptive 2-tap DFE to achieve the compensation for a Nyquist...
In this paper a high order temperature compensation current reference circuit was proposed, which is accomplished by two current source with opposite temperature coefficients (TC) to obtain a smaller TC. The proposed circuit with a simple structure designed in Global Foundries 0.18μm CMOS process, achieving a temperature coefficient of 30.7ppm/°C in the range of −50∼120°C, and the quiescent current...
The 10Gbase-KR protocol is widely used to accomplish the high speed data conversion in the Ethernet area. This paper presents a design of the critical controller in the physical coding sublayer based on the 10Gbase-KR. In order to satisfy the demand of the high speed data conversion, the scrambler and descrambler are specially designed to work in a parallel mode. The post-synthesis simulation results...
An innovative active-quenching circuit for single photon avalanche diode is presented. A differential amplification circuit based on offset control scheme is adopted to realize rapid avalanche signal discrimination. In order to save the die area, a voltage-controlled transistor acting as a sensing resistance is used. Compared with other traditional circuits, the proposed circuit does not need reference...
A novel current mirror sensing based multi-phase current balance developed in Global Foundry 0.18μm CMOS process was presented in this paper. Different from conventional current mirror sensing method, a new bypass branch was added to make the sample signal more accurate in high switching frequency situation. The method was realized in a 2.5MHz four-phase buck converter. As the simulation result shows,...
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