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In this paper we present a self-timed, power proportional, 32-bit ripple-carry adder design using a state-of-the art cell library. The cell library implements a new transistor sizing strategy for subthreshold in a commercial 65 nm low power process. Simulation results show improvements in performance and energy per cycle when compared to a fixed-period design. The adder has applications in the internet...
A framework to assess the reliability of an automotive motor controller with power electronics is presented in this paper. In specific, the significant power electronic device inside the controller, i.e., Insulated Gate Bipolar Transistor (IGBT), is modeled and its operation is simulated using the Matlab/Simulink tool. By computing its thermal behavior one can predict the impact of thermo-mechanical...
The demands of high-speed and power-efficient systems have resulted into the emergence of the approximate computing. Existing approximate circuits as well as stochastic techniques have shown promising advances in improving various figures of merit. However, a through fair comparison of arithmetic units still remains an issue which has not been studied. This paper reviews the prerequisites for a fair...
Lately, the advancement in circuit technology combined with the design of low cost embedded devices have resulted in an infiltration of the latter into everyday humans' lives. To exploit the full potential of ubiquitous embedded devices, a network is used for their inter-communication, offering advanced real-time monitoring. This paradigm, known as Internet of Things (IoT), is steadily consolidated...
Cellular Automata (CAs) is a well-known parallel, bio-inspired, computational model. It is based on the capability of simpler, locally interacting units, i.e. the CAs cells, to evolve in time, giving rise to emergent computation, suitable to model physical system behavior, prediction of natural phenomena and multi-dimensional problem solutions. Moreover, at the same time CAs constitute a promising...
This paper presents the energy analysis of capacitive adiabatic logic (CAL) based on gap-closing MEMS devices. CAL uses variable capacitance components instead of transistor elements to have a new balance between on- and off-state losses. Ultra-low power consumption in CAL requires an energy efficient way for charging and discharging of the variable capacitance. First, we investigate “pure” electrical...
This paper proposes a topology optimization method for dual-threshold (DT) independent-gate (IG) FinFET circuits. In the proposed method, a node extraction algorithm is developed to extract the characteristic nodes of a BDD expression, which are suitable to be realized with the compact logic gates based on the DT IG FinFET devices, and then the equivalent replacement program that these extracted characteristic...
The simulation of aging induced degradation mechanisms is a challenging task during the design of digital systems. Parametrical degradations can be handled most accurately at TCAD level, as the physical models like [1] and [2] can be implemented directly. On the other hand, timing failures caused by such degradations cannot be assessed exactly lower than Register Transfer Level (RTL), where the notion...
In this paper, a methodology for substrate noise reduction in mixed-signal integrated circuits (IC) in lightly doped substrates is proposed. The methodology is based on separating a digital aggressor circuitry into two power domains, one closer and one more distant from the victim. By proper assignment of digital modules in one of those two domains, substrate noise sensed by an analog victim is reduced...
Toward integrating memristors in CMOS-based designs flexible prototyping environments are necessary. However, research in digital memristive systems so far lacks an adequate testing platform for real world devices. To achieve better handson experience, we developed a flexible FPGA-based solution which allows to link memristors with arbitrary compute units such as MIPS, ARM processor cores or own custom...
3D integration is one of the most promising solutions for the scaling of future integrated circuits (ICs). Nevertheless, the 2D metal wires and 3D through silicon vias (TSVs) are frequently performance bottlenecks of 3D ICs, due to their high capacitive crosstalk, which can be reduced by a coding approach. In this work we show that existing TSV crosstalk avoidance codes (CACs) are impractical for...
For efficient design of digital circuits operating under wide range of voltage voltages, RTN model incorporating the dependencies of both the gate area and supply voltage are required. In this paper, we characterize the delay distributions due to RTN under different supply voltages. The delay distributions are then converted to threshold voltage distributions by statistical analysis. Measurement results...
The Internet of Things revolution requires long-battery-lifetime, autonomous end-nodes capable of probing the environment from multiple sensors and transmit it wirelessly after data-fusion, recognition, and classification. Duty-cycling is a well-known approach to extend battery lifetime: it allows to keep the hardware resources of the micro-controller implementing the end-node (MCUs) in sleep mode...
ASICs for Stochastic Computing conditions are designed for higher energy-efficiency or performance by sacrificing computational accuracy due to intentional circuit timing violations. To optimize the stochastic gate-level circuit behavior of a specific design, iterative timing analysis campaigns have to be carried out for a variety of chip temperature- and supply voltage-dependent timing corner cases...
Environmental temperature variations, as well as process variations, have a detrimental effect on performance and reliability of embedded systems implemented with deep-sub micron technologies. This sensitivity significantly increases in ultra-low-power (ULP) devices that operate in near-threshold, due to the magnification of process variations and to the strong thermal inversion that affects advanced...
In digital logic circuits, unconstrained scan tests are known to evoke much higher switching activity than functional modes. To create test conditions which are as similar as possible to functional modes, today's ATPG tools have knobs to constrain the switching activity of the generated test to a user-defined functional (= lower) level. Two-dimensional system chips (SoCs) and three-dimensional stacked...
Memristors have extended their influence beyond memory to logic and in-memory computing. Memristive logic design, the methodology of designing logic circuits using memristors, is an emerging concept whose growth is fueled by the quest for energy efficient computing systems. As a result, many memristive logic families have evolved with different attributes, and a mature comparison among them is needed...
Ultra-deep sub-micron technology is shifting the design paradigm from area optimization to power optimization. In the context of Network-on-Chip (NoC) based design, energy consumption due to data transfer among network nodes is no longer negligible. Starting from the observation that, among the two brain hemispheres around 1 out of 106 synapses are active at the same time, in this paper we propose...
In this paper, we discuss the architecture exploration of a Neuromorphic Signal Processing Integrated Circuit using Precise Timing. This device is intended to fulfill the role of a Digital Signal Processor in the spiking domain, becoming an essential tool to Spiking Neuromorphic Sensors such as Dynamic Vision Sensors. Our approach is based on the use of Spiking Neural Networks with preset topology...
Application requirements along with the unceasing demand for ever-higher scale of device integration, has driven technology towards an aggressive downscaling of transistor dimensions. This development is confronted with variability challenges, mainly the growing susceptibility to time-zero and time-dependent variations. To model such threats and estimate their impact on a system's operation, the reliability...
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