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This work presents a System-on-Chip designed for Energy-Harvested applications. It embeds an ARM® Cortex®-M0+ microcontroller, 4KB RAM, 4KB ROM, an ultra-low power frequency synthesizer, a custom power switch, and a Power Management Unit enabling Active and Sleep modes. The system fabricated in 28 nm FD-SOI technology achieves 2.7pJ/cycle at 16 MHz during active mode, and the core consumes 4.3 nW...
This paper presents a timing error masking-aware ARM Cortex M0 microcontroller system. Timing errors are detected through a timing error detection strategy, consisting of a soft edge flip-flop combined with a transition detector and an error latch. The time borrowing realized through soft edge flip-flops allows data to propagate after the clock edge (timing error masking). Thus operation at the point-of-first-failure...
We present a co-design approach of a near-threshold voltage adaptive microprocessor and power-management unit (PMU). It consists of (i) a microprocessor with in-situ error detection and correction; (ii) an integrated 63-ratio switched-capacitor DC-DC converter; and (iii) an error-based controller which regulates the timing error rate of microprocessor directly instead of indirectly through regulating...
A 1.25GS/s 7b single-channel SAR ADC is presented with an SNDR/SFDR of 41.4dB/51dB at low frequencies, while the SNDR/SFDR at Nyquist are 40.1dB/52dB and remain still 36.4dB/50.1dB at 5GHz. The high input frequency linearity is enabled by a fast bootstrap circuit for the input switch, while the high sampling rate, the highest among recently published >34dB SNDR single-channel SAR ADCs is achieved...
This paper presents a 2 GS/s 5-b single-channel SAR ADC in 28 nm CMOS. The ADC uses a gm-boosted StrongARM comparator to achieve the highest reported sampling frequency for a non-time-interleaved SAR ADC. Its high sampling frequency, large input signal capability and one clock cycle latency make the ADC suitable for time-interleaved, multi-stage and feedback ADC architectures. The ADC occupies 900...
A 43.6dB-SNDR 1-GS/s 8-bit single-channel successive-approximation-register (SAR) analog-to-digital converter (ADC) using coarse and fine comparators with fully background comparator offset calibration is presented. Low-power coarse comparators and low-noise fine comparators are both employed to improve the comparator power efficiency. Non-binary digital-to-analog converter (DAC) with redundancy is...
This paper presents a time-interleaved pipelined-SAR converter targeting a multi-band mobile communication receiver. The input buffer is based on a super-source follower and linearized by selecting a specific bias current and drain bias resistor. Time interleaved sampling time mismatch is resolved by using a common sample and hold circuit, and gain mismatch is corrected by fine tuning respective subADC...
A 12 b 600 MS/s 2 × TI SAR ADC achieving 60 dB SNDR at Nyquist is presented. Time-interleaving errors are calibrated in the background by using a linear but noisy reference ADC. A test chip demonstrates that interleaving spurs are reduced to below −70 dBFS using an off-chip least-mean-squares (LMS) algorithm. The reference ADC is an 8 b SAR with reduced sampling capacitance and input amplitude. This...
A class-AB and a class-J PAs for X-band phased array radar applications are presented. The class-AB fully-differential design features the cascade of a 8-bit PGA and a PA core, leading to a gain variation range of over 50 dB with a phase shift deviation of < 4° over a 25 dB attenuation range. The differential circuit shows 23 dB maximum gain, and 22 dBm saturated power at a PAE of 31%. Class-J...
An I/Q RF-DAC featuring two 6-bit DAC elements driven in quadrature, each with its own on-die antenna, and a total EIRP of 13.2 dBm, is demonstrated in a 45-nm SOI-CMOS technology. The 129–143-GHz carrier signal is first amplified by the 30-dB gain LO path and is directly modulated by the 12 baseband bit streams, without linear upconversion or power amplification. QPSK, 8-PSK, 16-QAM, 32-QAM, and...
This paper presents a multi-channel transmitter (TX) architecture that uses only a single bulk acoustic wave (BAW) resonator while covering 88 MHz of bandwidth. The proposed architecture overcomes the limited tuning range of a single BAW resonator by combining the BAW tuning range with a programmable integer-N frequency division and RF single-sideband (SSB) mixing approach. The single-BAW multi-channel...
This paper presents a 15-bit digital power amplifier (DPA) with 1.6W saturated output power. The topology of the polar switched-current DPA is discussed together with the architecture of the output transformer which is implemented in BEOL as well as in WLCSP metal layers. The chip is fabricated in a standard 28nm CMOS process and exhibits an EVM of 3.6%, E-UTRA ACLR of 34.1dB, output noise of −145...
An 8-way phased array TRX front-end with RF phase shifting and on-chip TR switching is implemented in 28nm CMOS . The TX OP1dB and RX NF are 10dBm and 6.8dB, respectively. The active phase shifter shows less than 5° phase resolution and amplitude errors within ±0.35dB. The 9.6mm2 chip consumes 231mW in RX and 508mW in TX mode from a 0.9 V supply. When combined with PCB antennas, a ±46° scan angle...
This paper presents a 60 GHz class-E digital power amplifier (DPA) that generates energy-efficient, non-constant envelope modulations up to 25 Gb/s. The DPA achieves a peak drain efficiency of 17.7% at a Vsat of 7.4 dBm. By means of direct digital amplitude modulation of the 6-bit output stage, the DPA produces error-free, high-order constellations (16-QAM, 32-QAM, 64-QAM) up to 5 GSym/s with error...
Real-time 3D ultrasonic imaging requires a matrix of transducer elements with a number of elements that readily exceeds the number of channels of a conventional imaging system. This paper presents an ASIC, realized in a high-voltage 0.18 μm BCDMOS process, that interfaces a piezo-electric transducer array of 24 × 40 elements, directly integrated on top of the ASIC, to an imaging system using only...
We report a system-on-chip (SoC) realised in 130nm CMOS for implantable telemetry systems and mobile health applications featuring 6 neural stimulation channels and acquisition circuits for 9× electrode-based recordings (ExG), 4×/32× photo-plethysmography (PPG), bio-impedance, and temperature. The SoC includes a low-power quad-core processor (34μW/MHz) with sophisticated power and clock management...
A low-voltage, ultra-low power sensor interface for electromyogram (EMG) signal acquisition is presented. The sensor interface consists of an amplifier and a SAR ADC that work from a 0.3V supply. The low-voltage amplifier topology provides a noise level of 26μVrms, 40dB gain and a state-of the art power efficiency factor (PEF) of 2.2 from a 20–425Hz bandwidth. Low-voltage supply improves the power...
This paper presents a low power, high resolution bio-impedance sensor IC for respiration monitoring application. It contains the dual path instrumentation amplifier (DPIA) including current reusing transconductance amplifier and high gain transimpedance amplifier for high resolution, low power and wide input range bio-impedance measurement. Measured results show that the proposed readout circuit has...
This paper presents an integrated fully differential current driver for wearable multi-frequency electrical impedance tomography (EIT). The integrated circuit (IC) comprises a wideband current driver (up to 500 kHz) functioning as the master for current sourcing, and a differential voltage receiver with common-mode feedback configuration as the slave for current sinking. The IC is fabricated in a...
Reference drivers for charge-redistribution SAR ADCs require significant area and/or power. In this work, a low-power and area-efficient passive reference-voltage driving scheme for charge-redistribution SAR ADCs is proposed. An on-chip decoupling capacitor is pre-charged to a reference voltage during tracking phase and utilized to drive the DAC passively during conversion. The reference-voltage drops...
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