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This paper describes the electrostatic discharge (ESD) failure caused by parasitic BJT in N-substrate process. The study of ESD failures in P-substrate process[1-3] has been a topic of increasing interest. Meanwhile N-substrate process, which may cause unexpected ESD failure, has hitherto received little attention. Through data analysis, unexpected ESD failure in N-substrate process may be attributed...
This paper reports three new delayer methods for TEM sample preparation with the benefit to locate the region of interest rapidly and efficiently. The experimental results showed that these methods can help to minimize the cycle time, decrease the cost and improve the sample quality.
In this paper, we performed accelerated degradation testing (ADT) of a certain type of driver IC under different humidity stress levels. We keep the drivers in storage under same temperature but different humidity; measure the determined sensitive parameter of the driver with fixed time interval, then model the degradation path to obtain the pseudo-failure lifetime. Finally, we analyze the test data...
This paper demonstrates integration non-destructive analysis tools solution of MEMS multi-bonding to inspect the fusion bonding interface and eutectic bonding interface to locate defect layers. This analytical study shows successful SAT (Scanning Acoustic Tomography) and IROM (Infrared Optical microscopy) inspection of MEMS multi-bonding single issue layer. The multi-bonding double layers were happened...
In this study, a comparison of the interfacial adhesion strength of Plasma Enhanced Chemical Vapor Deposition (PECVD) silicon nitride (SiN)/Cu and High-Density Plasma Chemical Vapor Deposition (HDP CVD) SiN/Cu was performed using the 4-Point-Bending (4PB) technique. Differences in critical energy release rate value Gc, which is an indicator of the interfacial adhesion strength, were observed. The...
This paper reports a study of transient behaviors of diode-triggered silicon-controlled rectifier (DTSCR) electrostatic discharging (ESD) protection structures for ultra-fast Charged Device Model (CDM) ESD protection. The DTSCR ESD protection structures, fabricated in a 28nm CMOS process, were characterized using a new combined Very Fast Transmission Line Pulse (VFTLP) testing and TCAD simulation...
With process technology development and circuit density rapidly increases, shrinkage of semiconductor device geometries has become extremely difficult to effectively analyze defect. Therefore, an exactness failure analysis process flow and technique need to be considered in order to analyze the failure mechanism, especially complex failure analysis such as failure of open/floating signal net in logic...
The clamped inductive turn-off failure of Silicon-on-Insulator Lateral Insulated Gate Bipolar Transistor (SOI-LIGBT) with multi-finger layout pattern is investigated in this paper. Firstly, the measurements of device failure under clamped inductive turn-off are discussed. Secondly, simulations are carried out to reproduce the failure by using Sentaurus TCAD. It is found that the failure origins from...
As the process of device is scaling down continually. Engineers are trying their best to challenge the limitations of physics in IC industry. However, power IC like power MOSFET and Insulated Gate Bipolar Transistor (IGBT) still have a high requirement despite device scale — downs. Here, we want to highlight a method to improve defect location in IGSS (Gate — Source leakage) failure, through this...
Recently, FInFET is introduced to deliver products with higher speeds and power efficiencies. Due to its 3D structure, FinFET results in complexity during the failure analysis process. Conventionally, the failure analysis (FA) starts with electrical failure analysis (EFA) to isolate the fault and follows by the physical failure analysis (PFA) to find the root cause. However, for the advanced technology,...
An electrostatic discharge (ESD) protection design by using stacked diodes and silicon-controlled rectifier (SCR) as power clamp is presented to protect a K-band low-noise-amplifier in nanoscale CMOS process. Experimental results show that the proposed design can achieve higher ESD robustness without degrading the radio-frequency (RF) performance. Based on its good performances during ESD stress and...
In this study, we establish the SDL (soft defect location) system based on the DALS module of new Hamamatsu Phemos1000 system to analyze the temperature sensitive failure. Our results show that the DALS module is a significant platform to establish the SDL system on because it can mark the defect spot synchronously with the laser scan, and with some external equipment added in, it can isolate the...
We have developed a new method to quantitatively evaluate the detectability for voids in bonded wafers by using ultrasonic inspection. The test sample for evaluation consists of bonded two Si wafers and has artificial voids between the wafers. The depths of these artificial voids are 5, 10, 20, and 170 nm. In this study, the evaluation was made by obtaining the images of artificial voids by using...
Successful failure isolation from front side becomes very expensive and time consuming as the technology nodes becoming increasingly difficult. Electro Optical Techniques, composed of Electro Optical Frequency Mapping (EOFM) and Probing (EOP), are dynamic optical analysis techniques. Most EOP/EOFM applications have focused on design debug or design characterization of integrated circuits (ICs), but...
Today's complex integrated circuits demand tight process control in manufacturing. In this paper, several case studies due to slight process deviation resulting in yield loss from marginal leakage failure were presented. While conventional fault isolation approach relies on the localization of exclusive laser induced or photon emission hotspot to highlight the defect location and pays little attention...
This work discusses visible light laser voltage probing (VIS-LVP) and gallium phosphide solid immersion lens (GaP SIL) research for Integrated Circuit (IC) analysis at Technische Universität Berlin. An overview of the challenges in connection with the ultra-precision fabrication of GaP SILs and their application is given. The use of visible light is not only opening a path for fault isolation in small...
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