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In this work, ESD immunity enhancement for the HV n-channel LDMOS with source-end discrete islands fabricated by a TSMC 0.25 μm 60 V process was investigated. An nLDMOS device always has poor ESD capability. If discrete n+ islands are formed in the source end of an nLDMOS transistor, the It2 value of this DUT is upgraded by 4.92% as compared with that of the reference nLDMOS. Meanwhile, if an nLDMOS...
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