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Traditional ESD protection program cannot meet requirements of higher ESD protection grade and parasitic parameter of protection devices when using V-by-One high-speed interface chip. This paper proposes an effective ESD protection program by way of reverse analysis and design of a VBO-based high-speed interface chip failure case. The program introduces a new SCR structure replacing the original diode...
MM (Machine Model) is an ESD test method used to test for robustness of the device against the ESD event which is induced by the running equipment in fabrication or testing procedure [1]. Due to zero resistance in the equivalent circuit, MM is difficult to simulate. In most cases, MM capability can be calculated from HBM (Human Body Model) result (MM ∼10∼20∗HBM) [2]. But in this study HBM can reach...
According to previous work about PESD optimization [1], there are some potential risks such as low breakdown voltage (VBD) and low holding voltage (Vh) can be improved for power-rail ESD application. Through drain region design with P-type concentration engineering, the enclosed P-Well in Deep N-Well (EW) in drain region was proposed with high ESD performance (HBM>8kV) and good turn-on efficiency...
In this work, ESD immunity enhancement for the HV n-channel LDMOS with source-end discrete islands fabricated by a TSMC 0.25 μm 60 V process was investigated. An nLDMOS device always has poor ESD capability. If discrete n+ islands are formed in the source end of an nLDMOS transistor, the It2 value of this DUT is upgraded by 4.92% as compared with that of the reference nLDMOS. Meanwhile, if an nLDMOS...
LIHT (Lack Injection of Hole Termination) structure is proposed and studied. Compared with conventional termination structure, the novel structure features a partial N-doped anode in the transition region and termination region instead of a whole P-doped anode. The LIHT structure stores less carries in the drift region of the transition region and termination region, in which holes concentration reduced...
An electrostatic discharge (ESD) protection design by using stacked diodes and silicon-controlled rectifier (SCR) as power clamp is presented to protect a K-band low-noise-amplifier in nanoscale CMOS process. Experimental results show that the proposed design can achieve higher ESD robustness without degrading the radio-frequency (RF) performance. Based on its good performances during ESD stress and...
The influence of forward current freewheeling time on the reverse recovery di/dt robustness of Superjunction (SJ) MOSFET body diode is investigated in detail. It is found that the maximum di/dt capability of body diode is improved dramatically with reducing the forward current freewheeling time. To explore this phenomenon, physical TCAD simulations and experiments have been carried out. It shows that...
3D-IC has been recognized as one of the technology solutions from More than Moore. Xilinx's 3D-IC FPGA has been well adopted by the industry since the first Virtex®-7 2000T introduced in 2011. In particular recently, data center requires large volume of 3D-IC for its applications. To fulfill the high demand effectively the best way is to provide the high yield and reliability 3D-IC product supply...
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