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A novel design consisting of a heterogeneous stacking of silicon control rectifier is proposed in this paper. A latch-up free design in a high voltage BCDMOS process is demonstrated. Structures based on this method are compared with conventionally stacked SCR structure. Comprehensive characterization, including DC and transmission line pulsing (TLP), is undertaken to demonstrate the performance.
Segmentation technique for optimizing the holding voltage of SCR is discussed and implemented in a 0.6μm SOI process. Based on the prior researches, the holding voltage of SCR is a key parameter for latch-up risk assessment. The segmented SCR with external resistor paralleled with the parasitic Ptub resistor is proposed by modifying the layout, and the holding voltage can be increased. The TLP characterization...
Electrochemical migration (ECM) pose a high reliability risk to semiconductor devices. In this study, an ECM caused electrical failure case detail was shared, relevant electrical failure & ECM mechanism was also analyzed. To verify the failure mechanism discussed in this paper, ECM process was simulated on the same chip substrate. Besides, for the first time, the effect of chloride ion concentration...
LIHT (Lack Injection of Hole Termination) structure is proposed and studied. Compared with conventional termination structure, the novel structure features a partial N-doped anode in the transition region and termination region instead of a whole P-doped anode. The LIHT structure stores less carries in the drift region of the transition region and termination region, in which holes concentration reduced...
In this paper, the influences of sandwiched structure trench on the latch-up reliability of the LIGBT with thick SOI substrate are investigated. Based on the influence mechanisms, a novel device structure with trench grounded is proposed, which can enhance the latch-up voltage by 24% with the other performance maintained. Further studies illustrate that the latch-up voltage would decrease dramatically...
In this paper, an improved LDPMOS_SCR without a LDPMOS structure (NonLDPMOS_SCR) is discussed, which is realized in 0.5-μm 5V/18V/24V CDMOS process. The theoretical analysis and transmission line pulse (TLP) testing system are used to predict and characterize the proposed ESD protection devices. According to the measurement results, compared with the normal LDPMOS_SCR, NonLDPMOS_SCR elevates the second...
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