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This paper presents a smart contact lens (SCL) sensor system for successive evaluation of tear evaporation. The proposed SCL system integrated with 3D technology is composed of tunable sensitivity sensor-readout circuitry, a tear sensor, and an antenna, and is embedded into a biocompatible hydrogel-based contact lens by a commercial manufacturing process. Moreover, the on-lens system can be addressed...
Counterfeit ICs pose a threat to designing secure and reliable electronic systems. To better detect and prevent counterfeit ICs from entering the supply chain, an eflash based powerless non-volatile sensor using floating-gate (FG) technology is demonstrated in a 0.35μm standard logic process. By exposing the FG to the environment, the proposed sensor can record any physical tamper attempt affecting...
We present a CMOS image sensor (CIS) with phase detection auto-focus (PDAF) in all pixels. The size of photodiode (PD) is 0.64μm by 1.28μm, the smallest ever reported and two PDs compose a single pixel. Inter PD isolation was fabricated by deep trench isolation (DTI) process in order to obtain an accurate AF performance. The layout and depth of DTI was optimized in order to eliminate side effects...
New methods were studied to reduce response time and threshold voltage drift of the FET-type hydrogen sensor. The advantages of the Pt-Ti-O gate over other sensor gate materials were demonstrated. Extending Langmuir's dissociative adsorption theory to non-equilibrium states enabled us to reduce the response time, and the negative gate bias operation with P-FET-type sensor reduced the drift. Thus,...
Three-dimensional (3D) fanout package stacking offers new levels of performance, high-density integration, and form factor advantages. Known-good fanout packages are stacked, and the vertical connection is built through Cu pillars in the molding area and solder bumps. Compared to existing TSV-based 3D integrated circuits (3DIC) technology, this solution reduces thermal crosstalk when integrating devices...
We demonstrate scaled high-Ge-content (HGC) strained SiGe pMOS FinFETs with very high short channel (SC) performance using a Replacement High-K/Metal Gate (RMG) flow, for the first time. A novel RMG gate stack process was introduced to create Ge-free interface-layer (IL) with excellent reliability and sub-threshold swing (SS) as low as 62mV/dec, the best reported to date for Si-cap-free SiGe FinFETs...
SiGe FinFET has been explored for its benefit of high current drivability provided by channel strain [1-5]. We have demonstrated SiGe CMOS FinFET at 10nm technology ground rules including epitaxial defectivity control, DC performance and reliability benefit [6-8]. One concern of SiGe FinFET is channel strain relaxation by fin cut process [9] inducing local layout effect (LLE), which is crucial for...
We report high performance extremely-thin-body (ETB) Ge-on-Insulator (GOI) pMOSFETs fabricated by a new Ge condensation process with minimized temperature cycles and slow cooling-down rate. This new condensation process effectively suppresses strain relaxation during Ge condensation and creates high compressive strain. By combining the highly-strained GOI substrates with a digital etching process,...
We investigate the mechanism of interfacial layer formation on Si1−xGex (0 < x < 0.5) channel and its correlation to hole mobility. It is found that the mobility degradation in low-Ge-content Si1−xGex (x < 0.2) pFETs is attributed to a Ge-rich top surface in the channel directly induced by interfacial layer formation. In addition, the depth profile of a Si-rich top surface in high-Ge-content...
A new methodology to measure the product-like AC stress of metal critical peak current was implemented in 16nm High-K Metal Gate (HKMG) FINFET process. Traditional TLP tester can only generate minimum 1ns pulse width stress, which is still in thermal diffusion metal burn out regime. The proposed method can generate minimum pulse width of 100ps stress waveform through on-die tunable pulse-width generator...
A method for on-chip extraction of random telegraph noise (RTN) parameters from transistors is proposed. Exploiting the nature of exponential distributed RTN events, the proposed circuit enables the automatic extraction of mean RTN time constants from a large array of small-area transistors. The on-chip data processing provides a simplified measurement infrastructure, reduces the measurement time...
In this paper we deeply investigate the dependence of BTI with transistor scaling. Unlike PBTI, NBTI is strongly enhanced in narrow devices like Nanowire or Finfet. We clearly prove by means of 3D electrostatic simulations that it is due to a defect density at the Sidewall (SW) of the transistor about 2.5 times higher than the one at the Top Surface (TS).
Self-heating effect (SHE) has become a significant concern for device performance, variability and reliability co-optimization due to more confined layout geometry and lower-thermal-conductivity materials adopted in advanced transistor technology, which substantially impacts the integrated circuit (IC)'s design schemes. In this work, a new methodology for evaluation of SHE in both digital and analog...
This paper highlights a 14nm Analog and RF technology based on a logic FinFET platform for the first time. An optimized RF device layout shows excellent Ft/Fmax of (314GHz/180GHz) and (285GHz/140GHz) for NFET and PFET respectively. A higher PFET RF performance compared to 28nm technology is due to a source/drain stressor mobility improvement. A benefit of better FinFET channel electrostatics can be...
RF-CMOS process employing 14nm FinFET technology is introduced for the first time and its RF performance is characterized. Compared with its 28nm planar counterpart, the optimized 14nm RF FinFET consumes 63% of DC power with 53% of device active area and 3.8 times higher intrinsic gain (gm/gds). Based on the 14 nm technology, VNCAP with higher cap density (8%) and Q-factor (23%) is also verified for...
10nm 2nd generation BEOL technology is described with an optimized illumination system and multi-patterning lithography. While the optimized illumination system offered a possibility to pattern reduced metal pitches in the preferred orientation, difficulties of T-T and T-S patterning still remained. It was overcome by increasing the number of available multi-patterning colors from 2 to 4. First-ever...
We report a circular-shape monolithic transistor-antenna (trantenna) for high-performance plasmonic terahertz (THz) detector. By designing an asymmetric transistor on a ring-type metal-gate structure, more enhanced (45 times) channel charge asymmetry has been obtained in comparison with a bar-type asymmetric transistor of our previous work. In addition, by exploiting ring-type transistor itself as...
For beyond 7 nm node BEOL, line resistance (R) is assessed among four metallization schemes: Ru; Co; Cu with TaN/Ru barrier, and Cu with through-cobalt self-forming barrier (tCoSFB) [1]. Line-R vs. linewidth of Cu fine wires with TaN/Ru barrier crosses over with barrier-less Ru and Co wires for beyond-7 nm node dimensions, whereas Cu with tCoSFB remains competitive, with the lowest line R for 7 nm...
Ge n- and p-FinFETs with different interfacial layer ferroelectric HfZrOx (IL-FE-HZO) gate stacks have been demonstrated systematically by various annealing conditions for the first time. Microwave annealing (MWA) not only shows enhanced FE characteristics but also suppresses the gate leakage and Ge interdiffusion compared with conventional rapid thermal annealing (RTA). While HZO on Al2O3 IL results...
We report, for the first time, a gate last process, used to fabricate Negative Capacitance field effect transistors (NCFETs) with Hf0.5Zr0.5O2 (HZO) as ferroelectric (FE) dielectric in a metal/ferroelectric/insulator/semiconductor (MFIS) configuration. Long channel NCFET's with HZO thickness down to 5 nm exhibit consistent switching behavior with switching slope (SSrev) below kT/q over four decades...
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