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This paper describes a complete process/design co-optimization methodology based on Fully Depleted SOI (FDSOI) technology. A process optimization is detailed through significant effective capacitance reduction, in order to optimize jointly frequency/leakage ratio and high frequency performances. In this objective, an efficient and low cost offset-spacers morphology has been designed to achieve maximum...
High crystal quality ultrathin Ge and Ge0.96Sn0.04 channels are epitaxially grown on SOI and Si bulk, respectively, and high mobility pMOSFETs are fabricated. Low-temperature Si2H6 passivation of Ge and GeSn is utilized to form a high quality SiO2/Si interfacial layer between the high-κ dielectric and channels, leading to a substantial reduction of Dit. Ge and GeSn pMOSFETs achieve the improved μeff...
In this work, we present our experimental results on Si GAA NW TFET inverters. The ambipolarity of both n- and p-TFETs was successfully suppressed by employing a drain spacer to create an intrinsic Si region between the drain and the gate, the so-called drain-gate underlap. The complementary TFET inverters show a steep transition between high/low states. Compared with the ambipolar TFET inverter,...
In recent years, GaN power HEMTs are gaining acceptance in power electronic applications. However, the implementation of Class D audio power amplifiers application using GaN power HEMTs has not been widely studied. This paper studies the performance of two open-loop 25 W Class D audio power amplifiers with GaN and silicon output stages using a Pulse Density Modulation (PDM) scheme. Comparisons of...
In this work, we studied the advanced nanofabrication technologies including electron beam lithography, blockcopolymer-based self assembly fabrication and their combination lithography, that is, directed self assembly (DSA). Nanostructures with a size of 10 nm order were successfully fabricated using these technologies. We attempted to further incorporate these nanostructures fabricated by these advanced...
A combined wafer bonding method consist of spot pressing bonding technique and water glass adhesive layer is proposed. The mechanism of water glass bonding is investigated, and the two major factors in this bonding method: surface energy and voids formation has also been discussed.
Germanium (Ge) is not a new material but now spotlighted for beyond Si-scaled CMOS. Ge p-MOSFETs have been well investigated and its high performance has so far been demonstrated. On the contrary, an achievement of high electron mobility Ge n-MOSFETs is quite challenging due to a large amount of interface states near the conduction band edge. So, we first discuss how to overcome “intrinsic challenges...
This review demonstrates the potential of low frequency noise diagnostics for the characterization of Ge-based and III–V technologies processed on a Si platform. The analysis of traps in both gate dielectrics and semiconductor films is illustrated for state-of-the-art devices.
The hexagonally ordered patterns by self-assembly of block copolymer with diameter and spacing down to 23 nm and 15 nm, respectively, are capable of producing Si nanopores with high aspect ratio from patterned Au film. The etching feature size seriously depends on the block copolymer pattern template. The prepared nanostructure patterns were used as substrates for surface enhanced Raman spectroscopy...
A simple and effective method to grow GaN on Si substrates has been achieved. The method that GaN comes out from a submicron and deep hole with nearly zero dislocations above the mask is demonstrated. This work proves that reducing the epitaxy area by using mask and increasing the depth to width ratio of pattern contribute to filtering the dislocations and improving the quality of GaN.
This paper presents an overview of three works about graphene-based resistive random access memory (RRAM). The fabrication, device performance and working mechanism of graphene-inserted electrode RRAM, RRAM based on laser-scribed reduced graphene and gate-controlled graphene-electrode RRAM are introduced. This work may inspire new design of high-performance RRAM based on two-dimensional material and...
The scaling behavior of MOSFETs based on two-dimensional (2D) materials is investigated by means of numerical simulation and analytical modeling. Due to their ultimate thinness, 2D channel materials like MoS2 are perfectly suited to push the scaling limits beyond those of silicon. The electrostatic integrity of 2D transistors is governed by the chosen device architecture, substrate material, and gate...
To date, gate stacks for high mobility semiconductors like Ge and InGaAs have been generally designed to minimise their interfacial trap density, and thus include an Al oxide layer diffusion barrier as a component. However, this is now known to lead to reduced reliability. The source of the problem is discussed and possible solutions based on an AlN or AlON layer component are suggested instead. First,...
The evolutionary process of nanoscale FinFET channel was investigated under hydrogen thermal treatment using kinetic Monte Carlo (KMC) simulation. We adopt appropriate activation energy to analyze the influence of hydrogen treatment temperatures and time on fin structure. Line edge roughness (LER) of silicon fin structure is effectively reduced in present KMC model. Our results indicate that optimized...
Silicon interposer based 2.5D IC can realize heterogeneous integration and is effective to implement an electro-optical system. In this paper, we analyze the CPW structure transmission line on silicon interposer for high speed electro-optical system. The RDL-TSV-RDL transmission structure is used to reduce the resonance. An optimization method is proposed to improve the performance of the RDL-TSV-RDL...
In MEMS realization of high frequency ultrasonic array transducer, electrical impedance matching may become difficult for the reason of the miniaturization of the piezo-array elements. In this study, the electrical impedance of the array elements is estimated first by using KLM model, and then calculated by using finite elements method (FEM), in the case of a LiNbO3 based 30MHz array transducer. The...
This paper presents an overview of recent developments in extending the temperature range capability of Mextram, an industry standard bipolar transistor compact model.
We present a systematic study of the impact of strain on off-state leakage current, using experimental data and ab-initio calculations. We developed new models to account for the impact of strain on band-to-band tunneling and trap-assisted tunneling in silicon. We observe that the strain can dramatically increase the leakage current, depending on the type of tunneling involved. We predict that 1%...
Graphene is coupled with silicon quantum dots (Si QDs) on the top of bulk Si to form a hybrid photodetector. SiQDs cause the built-in potential of the graphene/Si Schottky junction to increase. Si QDs also significantly reduce the optical reflection of the photodetector. Both of the electrical and optical contributions of SiQDs enable the superior performance of the photodetector.
In graphene FETs, the work function (WF) of electrode materials has remarkable influence on contact properties of Metal/Graphene(M/G). MoOx is a material with extremely high WF, when inserting nanoscale MoOx(x<3) thin layer between the interface of source/drain electrode and graphene in graphene FETs, acting as an efficient hole injection layer, MoOx can induce p-doping to graphene and therefore...
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