The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Efficient handling of faults during operation is highly dependent on the interval (latency) from the time embedded instruments detect errors to the time when the fault manager localizes the errors. Detection and localization latencies are dependent on the network connecting fault-monitoring instruments to the fault manager. The network can be dedicated to fault-monitoring data, or used for functional...
Physical unclonable functions (PUFs), are a new type of physical security primitive which enable digital identifiers to be extracted from devices, such as field programmable gate arrays (FPGAs) or application specific integrated circuits (ASICs). Due to their flexibility and lower time to market, FPGAs are increasingly used for many applications. Arbiter PUFs (APUFs) are among the most widely studied...
Sample Adaptive Offset (SAO) is a new tool added in latest video coding standard (HEVC) to achieve better coding efficiency resulting in higher visual quality. In this paper, we propose efficient and high performance VLSI architecture as well as data transfer scheme for SAO decoder that can work in a pipelined manner achieving 4K (Ultra-HD) resolution at 60 fps in video codec engine. The proposed...
A novel high-speed single-ended D flip-flop based on a SR(set/reset)-type latch is presented in this paper. The SR-type latch is adapted to implement a dynamic stage for high-speed operation and modified to add a scan mux without setup time degradation on a data path. The proposed flip-flop enables to achieve the high-speed operation having the comparable hold time characteristics to a conventional...
Sample preparation is one of the most crucial processes in most biochemical applications. Reagents are repeatedly diluted in an appropriate sequence to get a target solution with a specific concentration value. For flow-based microfluidic biochips (FMFBs), several research works have been proposed for reactant minimization. In this paper, we propose the first sample preparation algorithm for microfluidic...
This paper presents a multiplication reduction technique through near-zero approximation, enabling embedded learning in resource-constrained IoT devices. The intrinsic resilience of neural network and the sparsity of data are identified and utilized. Based on the analysis of leading zero counting and adjustable threshold, intentional approximation is applied to reduce near-zero multiplications. By...
Monitoring and tracking of IP traffic flows are essential for network services (i.e. packet forwarding). Packet header lookup is the main part of flow identification by determining the predefined matching action for each incoming flow. In this paper, an improved header lookup and flow rule update solution is investigated. A detailed study of several well-known lookup algorithms reveals that searching...
Cortical algorithms, inspired by the neocortex, promise to outperform conventional algorithms in unsupervised learning tasks, i.e. with unlabeled data. The aim of the work reported in this paper was to design and implement an application specific integrated circuit (ASIC) having a massive speedup of a cortical algorithm, as compared with a CPU baseline. This ASIC is designed to implement a scaled-down...
Analog-to-Digital Converters (ADCs) are essential blocks in digital signal processing (DSP) systems, software defined radio receivers (SDRs), and portable data acquisition systems. This paper introduces an 8-bit Time-based Analog to Digital Converter (T-ADC). This T-ADC utilizes an inherited sample and hold required to eliminate the dedicated power hungry sample and hold circuit. Moreover, a new design...
A folding multiplier tailored to subthreshold operation is presented for ultra-low-power en/decryption in SOC. The multiplier is composed of radix-4 booth encoder and two 544×16 bit partial product reduction tree arrays and reconfigurable data paths. The folding architecture can be configured for multiple multiplications with different bit size. Novel 6-2 compressors are applied to the reduction tree...
Flash memory is widely used, especially for mobile applications, as nonvolatile memory storage. In this paper, we present a Flash memory design based on Silicon on Ferroelectric-Insulator FET (SOFFET) device. This device has shown tremendous potential for various ultra-low-power (ULP) applications. SOFFET has the potential to provide high performance, multi-VT design, strong threshold voltage control,...
In this paper, a hardware ASIC implementation of the Numenta Hierarchical Temporal Memory (HTM) algorithm is presented. Each column in the neural network is implemented as a processing element (PE). Neuron cells in columns are built as identical cell modules. Dedicated register files for each module cell are employed to replace the conventional centralized memory organization. A complete neural network...
System-on-Chips (SoC) are being used to realize multipurpose devices such as mobile phones, consumer electronics which can connect over the internet. The design process including the physical design for an application specific SoC has become more complex due to large number of distinct functional modules. Existing physical design flow usually needs many iterations for successful design closure. In...
Many-Core System-on-Chips (MCSoCs) require efficient task migration approach in order to reach system performance objectives such as load balancing, communication optimization, fault tolerance, and temperature control. In this paper an efficient self-aware migration approach is introduced for NoC-based MCSoCs using a centralized feedback controller in order to control the congestion over the system...
Low-cost optical interconnects are playing an important role in sustaining the exponential growth in data center demand and to support the future internet-of-things cloud infrastructure. These chip-scale optical transceiver systems are integrated using two-chip bonding solution of CMOS electronic die with a silicon photonic die. In this work, modeling of the critical bond-wire is performed with electromagnetic...
A novel Jitter Cancellation Circuit (JCC) that reduces deterministic clock jitter induced by supply noise is designed. High Speed IO interface circuits require low deterministic clock jitter in order to meet the timing budget. Supply noise is a primary contributor of deterministic jitter. As data rates are scaling to higher frequencies, the acceptable jitter due to supply noise is decreasing. For...
In recent studies of ultrasound imaging systems, successive approximation register (SAR) analog-to-digital converters (ADCs) are suggested as an alternative architecture for low-power ultrasound receiver integrated circuits. However, the sampling period of a high-speed SAR ADC is very short - less than a few nanoseconds. This results in the need of a very wide unity-gain bandwidth of the amplifier...
A physical operation-based drain current model is developed for novel avalanche ISFET (A-ISFET). Mobility degradation effect has been included into the model. The avalanche breakdown effects are modeled by using a previously developed impact ionization based finite multiplication breakdown model. Comparisons are made with SPICE simulation and experimental measured results, and a very good match is...
An ultra-low power voltage-to-time converter (VTC) circuit is proposed. The VTC circuit is compatible with wide range of applications (i.e. sensors, integrated DC-DC voltage converters) especially for time-based analog-to-digital converters (T-ADCs). In T-ADCs, the input voltage signal is first converted into a delay pulse using the VTC circuit, then this delay signal is converted into a digital code...
System-on-Chips designed for modern applications combine a large number of highly integrated Analog, Digital and Mixed-signal circuits. As we approach smaller technology nodes, semiconductor mask costs rise higher and higher. Thus the need to achieve first pass Silicon is even higher, so as to keep non-recurring engineering cost at a minimum, and eliminate Silicon debug time and mask re-spin costs...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.