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A novel Jitter Cancellation Circuit (JCC) that reduces deterministic clock jitter induced by supply noise is designed. High Speed IO interface circuits require low deterministic clock jitter in order to meet the timing budget. Supply noise is a primary contributor of deterministic jitter. As data rates are scaling to higher frequencies, the acceptable jitter due to supply noise is decreasing. For...
In clock and data recovery system of high speed IO, the phase of the clock for data sampler needs fine resolution control so that the incoming data can be sampled at a time point with the best signal-to-noise ratio. A phase interpolator (PI) is normally used as a phase shifter (or phase rotator) to generate an output clock whose phase is precisely controlled. In this paper we present a novel control...
This paper presents the design of fully differential injection locked frequency divider (ILFD) using area efficient inter-coupled differential injection enhancement of input signal. Fabricated in 65nm CMOS process technology, the proposed inter-coupled differential injection enhanced ILFD achieves twice the locking range with half the area in comparison with the single-ended inductor injection enhancement...
An Itanium® processor implemented in 32 nm CMOS with nine layers of Cu contains 3.1 billion transistors. The die measures 18.2 mm by 29.9 mm. The processor has eight multi-threaded cores, a ring based system interface and combined cache on the die is 50 MB. High-speed links allow for peak processor-to-processor bandwidth of up to 128 GB/s and memory bandwidth of up to 45 GB/s.
This paper presents a high performance wideband amplifier and justifies the performance with the aid of measurement results. The amplifier consumes very low power about 6.8mW from a supply voltage of 1.8V. The amplifier is designed using a cross coupled cascode topology to improve the Gain and Bandwidth. The design is implemented in a 0.18μm SiGe BiCMOS process (ft = 200GHz) with 9.3dB small signal...
A fully integrated fundamental and push-push voltage controlled oscillators (VCOs) working in K-band with a large tuning range and a low phase noise fabricated in a 0.18 µm SiGe BiCMOS technology is presented. To achieve a wide tuning range while maintaining a low VCO tuning sensitivity (Kvco), the coupled LC tanks and digital tuning capacitors are used. The VCOs achieve a frequency tuning range (FTR)...
This paper presents a compact microstrip bandpass filter (BPF) with separate electric and magnetic coupling paths (SEMCPs) for 60 GHz applications. Either electric or magnetic coupling can be dominant in the total electromagnetic coupling, while the location of transmission zeros differs. The proposed fourth-order BPF is designed based on two metal layers of a 85 µm LTCC substrate. Without any via...
A fully integrated voltage-controlled oscillator (VCO) working in K-band with a large tuning range and a low phase noise fabricated in a 0.18 µm SiGe BiCMOS technology is presented. To achieve a wide tuning range while keeping a low VCO tuning sensitivity (KVCO), the coupled LC tanks are used. The VCO achieves figures of merit (FOMs) greater than −180 dBc/Hz for both phase noise and tuning range with...
A 12-Gb/s transceiver in 32-nm bulk CMOS in described. Features include an 8.8–12.4-GHz LC-PLL with 0.4-ps jitter; a full-swing DLL and phase interpolator with LSB=2.6 ps and DNL≪1.2 ps; a 4.2-mW receiver front end with de-muxing comparator and precharge removal latch; and an all-digital duty cycle correction (DCC) loop. The transceiver receives and transmits PRBS23 data at 12 Gb/s with BER≪10−12...
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