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A detailed statistical characterization of drain current local and global variability in sub 15nm gate length Si/SiGe Trigate NW pMOSFETs is carried out. An analytical mismatch model is used to extract the main matching parameters. Our results indicate that, despite their very aggressive dimensions, such devices maintain relatively good variability performance.
The interaction between strain and border traps in short-channel InGaAs NW MOSFETs is investigated through full-quantum 3D simulations based on a k·p Hamiltonian. Traps induce a sizable degradation of the ON-current, which can be recovered through the application of a suitable strain, provided the quantization effects, which increase by scaling the NW lateral size, do not become too large.
In this paper, we report an accurate physics-based compact model for monolayer Graphene Field-Effect Transistors (GFETs) based on the density of states (DOS) of monolayer graphene. The charge-based model computes the total current considering a branch separation between the electron and hole contributions preserving a good accuracy near the Dirac point. The effect of back-gate is included in the charge...
Integration of isolated LDMOS transistors in smart power process is subjected to bipolar parasitics due to multi layers constructions that are needed for high voltage operation. These parasitics need to be minimized to assure proper circuit functionality. Several approaches for parasitics reduction are suggested: DTI (Deep Trench Isolation) module optimization, NLDMOS and PLDMOS device construction...
In this paper we present an advanced methodology for effective 3-D device electrothermal simulation of power structures and power integrated circuits. The proposed electrothermal simulation is based on direct interconnection of a 3-D FEM thermal model and electrical circuit model of the device using a mixed-mode setup supported in Synopsys TCAD Sentaurus environment. This approach combines the speed...
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